diff --git a/Basys3_Master.xdc b/Basys3_Master.xdc index aa7b507..d901b12 100644 --- a/Basys3_Master.xdc +++ b/Basys3_Master.xdc @@ -237,35 +237,35 @@ set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] -##VGA Connector -#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] -#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] -#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] -#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] -#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] -#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] -#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] -#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] -#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] -#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] -#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] -#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] - #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] -#set_property PACKAGE_PIN P19 [get_ports Hsync] - #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] -#set_property PACKAGE_PIN R19 [get_ports Vsync] - #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] +#VGA Connector +set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +set_property PACKAGE_PIN P19 [get_ports Hsync] + set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +set_property PACKAGE_PIN R19 [get_ports Vsync] + set_property IOSTANDARD LVCMOS33 [get_ports Vsync] ##USB-RS232 Interface diff --git a/horizontal_counter.v b/horizontal_counter.v new file mode 100644 index 0000000..9148f6f --- /dev/null +++ b/horizontal_counter.v @@ -0,0 +1,89 @@ +///////////////////////////////////////////////////////////////// +// Author - Imants Pulkstenis +// Date - 04.04.2020 +// Project name - Audio FFT on FPGA +// Module name - horizontal counter +// +// Detailed module description: +// +// +// +// Revision: +// A - initial design +// B - +// C - +// +/////////////////////////////////////////////////////////////////// +module horizontal_counter #( + parameter + HSYNC_CLKS = 800, + HSYNC_DISPLAY = 640, + HSYNC_PULSE = 96, + HSYNC_FRONT_PORCH = 16, + HSYNC_BACK_PORCH = 48 + )( + input clk, + output o_Hsync, + output o_h_display, + output [9:0] o_h_pixel + ); +//----------Internal registers, constants and wariables----- +reg hsync_reg = 1'b1; +reg [9:0] counter_reg = 'h0; +reg [9:0] counter_pixel_reg = 'h0; +reg [2:0] r_state=HS_FRONT_PORCH, r_next=HS_FRONT_PORCH; +localparam [2:0] HS_FRONT_PORCH = 'h0, + HS_PULSE = 'h1, + HS_BACK_PORCH = 'h2, + HS_DISPLAY = 'h3; + +//---------state register sequential always block----------- +always @(posedge clk ) begin + r_state <= r_next; +end +//----next state & outputs, combinational always block------ + + +always@(posedge clk) begin + counter_reg <= counter_reg + 1; + + case (r_state) + HS_FRONT_PORCH: begin + hsync_reg <= 1'b1; + if(counter_reg == HSYNC_FRONT_PORCH - 2) + r_next <= HS_PULSE; + end + HS_PULSE:begin + hsync_reg <= 1'b0; + if(counter_reg == HSYNC_FRONT_PORCH + + HSYNC_PULSE - 2) + r_next <= HS_BACK_PORCH; + end + HS_BACK_PORCH:begin + hsync_reg <= 1'b1; + if(counter_reg == HSYNC_FRONT_PORCH + + HSYNC_PULSE + + HSYNC_BACK_PORCH - 2) begin + r_next <= HS_DISPLAY; + counter_pixel_reg <= 'h0; + end + end + HS_DISPLAY:begin + hsync_reg <= 1'b1; + counter_pixel_reg <= counter_pixel_reg + 1; + if(counter_reg == HSYNC_FRONT_PORCH + + HSYNC_PULSE + + HSYNC_BACK_PORCH + + HSYNC_DISPLAY - 1) begin + r_next <= HS_FRONT_PORCH; + counter_reg <= 'h0; + end + end + endcase +end + +assign o_Hsync = hsync_reg; +assign o_h_display = (counter_pixel_reg >= 1 && counter_pixel_reg <= HSYNC_DISPLAY) ? 1'b1 : 1'b0 ; +assign o_h_pixel = counter_pixel_reg - 1 ; + +endmodule \ No newline at end of file diff --git a/top.v b/top.v index 8112e29..897795a 100644 --- a/top.v +++ b/top.v @@ -23,10 +23,16 @@ module top #( parameter input clk, input btnC, output [15:0] led, - + // 7 segment display output [6:0] seg, output dp, output [3:0] an, + //VGA inputs outputs + output [3:0] vgaRed, + output [3:0] vgaBlue, + output [3:0] vgaGreen, + output Hsync, + output Vsync, input [15:0] sw, // swiches on board to control effects output da_mclk, @@ -50,8 +56,8 @@ assign ad_mclk = master_clk; //output master clock to DAC //------internal wires and registers-------- wire master_clk; // 11.29 MHz master clock - -wire clk_50MHz; // +wire clk_50MHz; // 50 MHz clock +wire clk_25MHz; // 25 MHz clock wire w_reset; wire w_internal_reset; @@ -86,7 +92,8 @@ wire [d_width-1: 0] w_data_from_eff_sw1; clk_wiz_0 m_clk( .clk_in1(clk), .clk_out1(master_clk), // 11.29 MHz master clock for I2S - .clk_out2(clk_50MHz), // 25MHz main clock + .clk_out2(clk_50MHz), // 50MHz main clock + .clk_out3(clk_25MHz), // 25MHz main clock .locked(w_internal_reset), .reset(btnC) ); @@ -122,14 +129,14 @@ io_module #( // inputs to logic analyzer - .ch0(clk10k), - .ch1(da_sclk), - .ch2(da_lrck), - .ch3(da_sdin), - .ch4(master_clk), - .ch5(ad_sclk), - .ch6(ad_lrck), - .ch7(ad_sdout), + .ch0(Hsync), + .ch1(Vsync), + .ch2(), + .ch3(), + .ch4(), + .ch5(), + .ch6(), + .ch7(), .JXADC(JXADC) // output for logic analizer ); @@ -142,10 +149,36 @@ segment4x7 segment4x7( .dp(dp) // dot on 7segment display ); -clock_divider #(.WIDTH(9)) +clock_divider #(.WIDTH(11)) clock_divider7seg ( .clk_in(clk_50MHz), .clk_out(clk10k) ); +vga_module #( + // .ADDR_WIDTH(ADDR_WIDTH), + // .DATA_WIDTH(DATA_WIDTH), + // .DEPTH(DEPTH), + // .HSYNC_CLKS(HSYNC_CLKS), + // .HSYNC_DISPLAY(HSYNC_DISPLAY), + // .HSYNC_PULSE(HSYNC_PULSE), + // .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH), + // .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH), + // .VSYNC_LINES(VSYNC_LINES) , + // .VSYNC_DISPLAY(VSYNC_DISPLAY) , + // .VSYNC_PULSE(VSYNC_PULSE) , + // .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) , + // .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH) +) vga_module1 ( + .clk(clk_25MHz), + .o_vgaRed(vgaRed), + .o_vgaBlue(vgaBlue), + .o_vgaGreen(vgaGreen), + .o_Hsync(Hsync), + .o_Vsync(Vsync), + .o_display(), + .o_addr_rd(), + .i_data_rd() + ); + endmodule \ No newline at end of file diff --git a/vertical_counter.v b/vertical_counter.v new file mode 100644 index 0000000..f1c7199 --- /dev/null +++ b/vertical_counter.v @@ -0,0 +1,89 @@ +///////////////////////////////////////////////////////////////// +// Author - Imants Pulkstenis +// Date - 04.04.2020 +// Project name - Audio FFT on FPGA +// Module name - vertical counter +// +// Detailed module description: +// +// +// +// Revision: +// A - initial design +// B - +// C - +// +/////////////////////////////////////////////////////////////////// +module vertical_counter #( + parameter + VSYNC_LINES = 521, + VSYNC_DISPLAY = 480, + VSYNC_PULSE = 2, + VSYNC_FRONT_PORCH = 10, + VSYNC_BACK_PORCH = 29 + )( + //input clk, + input i_Hsync, + output o_Vsync, + output o_v_display, + output [8:0] o_v_line + ); +//----------Internal registers, constants and wariables----- +reg vsync_reg = 1'b1; +reg [9:0] counter_reg = 'h0; +reg [8:0] counter_line_reg = 'h0; +reg [2:0] r_state=VS_FRONT_PORCH, r_next=VS_FRONT_PORCH; +localparam [2:0] VS_FRONT_PORCH = 'h0, + VS_PULSE = 'h1, + VS_BACK_PORCH = 'h2, + VS_DISPLAY = 'h3; + +//---------state register sequential always block----------- +always @(posedge i_Hsync ) begin + r_state <= r_next; +end + +//----next state & outputs, combinational always block------ +always@(posedge i_Hsync) begin + counter_reg <= counter_reg + 1; + + case (r_state) + VS_FRONT_PORCH: begin + vsync_reg <= 1'b1; + if(counter_reg == VSYNC_FRONT_PORCH - 2) + r_next <= VS_PULSE; + end + VS_PULSE:begin + vsync_reg <= 1'b0; + if(counter_reg == VSYNC_FRONT_PORCH + + VSYNC_PULSE - 2) + r_next <= VS_BACK_PORCH; + end + VS_BACK_PORCH:begin + vsync_reg <= 1'b1; + if(counter_reg == VSYNC_FRONT_PORCH + + VSYNC_PULSE + + VSYNC_BACK_PORCH - 2) begin + r_next <= VS_DISPLAY; + counter_line_reg <= 'h0; + end + end + VS_DISPLAY:begin + vsync_reg <= 1'b1; + counter_line_reg <= counter_line_reg + 1; + if(counter_reg == VSYNC_FRONT_PORCH + + VSYNC_PULSE + + VSYNC_BACK_PORCH + + VSYNC_DISPLAY - 1) begin + r_next <= VS_FRONT_PORCH; + counter_reg <= 'h0; + end + end + endcase +end + +assign o_Vsync = vsync_reg; +assign o_v_display = (counter_line_reg >= 1 && counter_line_reg <= VSYNC_DISPLAY) ? 1'b1 : 1'b0 ; +assign o_v_line = counter_line_reg - 1 ; + +endmodule \ No newline at end of file diff --git a/vga_module.v b/vga_module.v new file mode 100644 index 0000000..dbd204e --- /dev/null +++ b/vga_module.v @@ -0,0 +1,92 @@ +///////////////////////////////////////////////////////////////// +// Author - Imants Pulkstenis +// Date - 04.04.2020 +// Project name - Audio FFT on FPGA +// Module name - VGA module +// +// Detailed module description: +// +// +// +// Revision: +// A - initial design +// B - +// C - +// +/////////////////////////////////////////////////////////////////// +module vga_module#( + parameter + ADDR_WIDTH = 17, + DATA_WIDTH = 12, + DEPTH = 76_800, // 307_200,// + HSYNC_CLKS = 800, + HSYNC_DISPLAY = 640, + HSYNC_PULSE = 96, + HSYNC_FRONT_PORCH = 16, + HSYNC_BACK_PORCH = 48, + VSYNC_LINES = 521, + VSYNC_DISPLAY = 480, + VSYNC_PULSE = 2, + VSYNC_FRONT_PORCH = 10, + VSYNC_BACK_PORCH = 29 + )( + input clk, + output [3:0] o_vgaRed, + output [3:0] o_vgaBlue, + output [3:0] o_vgaGreen, + output o_Hsync, + output o_Vsync, + output o_display, + output [ADDR_WIDTH-1:0] o_addr_rd, + input [DATA_WIDTH-1:0] i_data_rd + ); + +//-------Internal registers and wires-------------- +wire w_v_display; +wire w_h_display; +wire [9:0] pixel; +wire [8:0] line; + +//-------sub modules------------------------------- + +horizontal_counter #( + .HSYNC_CLKS(HSYNC_CLKS) , + .HSYNC_DISPLAY(HSYNC_DISPLAY) , + .HSYNC_PULSE(HSYNC_PULSE) , + .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH) , + .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH) + ) horizontal_counter1 ( + .clk(clk), + .o_Hsync(o_Hsync), + .o_h_display(w_h_display), + .o_h_pixel(pixel) + ); + +vertical_counter #( + .VSYNC_LINES(VSYNC_LINES) , + .VSYNC_DISPLAY(VSYNC_DISPLAY) , + .VSYNC_PULSE(VSYNC_PULSE) , + .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) , + .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH) + ) vertical_counter1 ( + //.clk(clk), + .i_Hsync(o_Hsync), + .o_Vsync(o_Vsync), + .o_v_display(w_v_display), + .o_v_line(line) + ); + +assign o_display = (w_v_display && w_h_display) ; +assign o_vgaRed = o_display ? i_data_rd[11:8] : 4'h0; +assign o_vgaBlue = o_display ? i_data_rd[3:0] : 4'h0; +assign o_vgaGreen = o_display ? i_data_rd[7:4] : 4'h0; + +/* +assign o_addr_rd = (((line*HSYNC_DISPLAY) + pixel + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ? + 'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + pixel[9:1] + 1 ; // get next pixel +*/ +assign o_addr_rd = + ((line[8:1]) * 'd320 ) + pixel[9:1];// + 1; + + +endmodule \ No newline at end of file