72 lines
2.7 KiB
VHDL
72 lines
2.7 KiB
VHDL
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-- Author - Imants Pulkstenis
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-- Date - 08.06.2020
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-- Project name - Lab work No3
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-- Module name - sin_gen_sum
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--
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-- Detailed module description:
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-- This is sum module adding signals from
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-- signal genrators
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-- and prepare this signal for FIR and IIR filter
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--
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-- Revision:
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-- A - initial design
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-- B - add overflow and unferflow check
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-- C - Remove sin_gen module out of this module
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-- add aditional inputs from top module
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-- to compensate changes
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity sin_gen_sum is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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port
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(
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clk : in std_logic; --100mhz clock
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--rst : in std_logic; --rst
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signal_in_one : in std_Logic_vector(data_width - 1 downto 0);
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signal_in_two : in std_Logic_vector(data_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0)
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);
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end sin_gen_sum;
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--define inside of the module
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architecture behavioral of sin_gen_sum is
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--define inside use signals
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signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word
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begin --define the operation of the module!
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--signal output
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signal_out <= std_logic_Vector(signal_summ);
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--adder
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process(clk)
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begin
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if rising_edge(clk) then
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if ((std_logic(signal_in_one(data_width-1)) and std_logic(signal_in_two(data_width-1))) = '1' ) and -- check is bouth numbers negative
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(signed(signal_in_one) + signed(signal_in_two) > x"0000" ) -- check sum is positive
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then --max negative
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signal_summ <= x"8000"; --underflow
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else if (std_logic(signal_in_one(data_width-1)) nor std_logic(signal_in_two(data_width-1))) = '1' and -- check is bouth numbers positive
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(signed(signal_in_one) + signed(signal_in_two) < x"0000" ) -- check sum is negative
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then --max positive
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signal_summ <= x"7fff"; --overflow
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else
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signal_summ <= signed(signal_in_one) + signed(signal_in_two); -- noramal sum
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end if;
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end if;
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end if;
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end process;
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end behavioral; |