143 lines
3.9 KiB
Verilog
143 lines
3.9 KiB
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - bin_7segment module for counter
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//
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// Detailed module description:
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//
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// This module 16bit input transforms
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// in 7-segment display induvidual segments
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// as outputs. Input clock is 1kHz and it
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// drives common anode for 7-segment display
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//
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module bin_7segment(
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input clk, // clock working with 1kHz
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input [15:0] in, // input
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output [6:0] seg, // individual segments of number
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output [3:0] an, // anode to select character
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output dp // dot on 7segment display
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);
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//-------------Internal Constants---------------------------
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parameter SIZE = 2;
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parameter [SIZE-1:0] ONE = 2'b00,
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TWO = 2'b01,
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THREE = 2'b10,
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FOUR = 2'b11;
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reg [SIZE-1:0] state=ONE, next=TWO;
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reg [6:0] r_nibble = 'b0 ;
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reg [3:0] r_an = 'b0 ;
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//---------State register sequential always block-----------
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always @(posedge clk ) begin
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state <= next;
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end
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//----Next state & outputs, combinational always block------
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always@(posedge clk)begin
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case(state)
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ONE : begin
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next <= TWO;
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r_an <= 4'b0001;
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case (in[3:0])
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4'h0 : r_nibble <= 7'b0111111;
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4'h1 : r_nibble <= 7'b0000110;
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4'h2 : r_nibble <= 7'b1011011;
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4'h3 : r_nibble <= 7'b1001111;
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4'h4 : r_nibble <= 7'b1100110;
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4'h5 : r_nibble <= 7'b1101101;
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4'h6 : r_nibble <= 7'b1111101;
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4'h7 : r_nibble <= 7'b0000111;
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4'h8 : r_nibble <= 7'b1111111;
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4'h9 : r_nibble <= 7'b1101111;
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4'ha : r_nibble <= 7'b1110111;
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4'hb : r_nibble <= 7'b1111100;
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4'hc : r_nibble <= 7'b0111001;
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4'hd : r_nibble <= 7'b1011110;
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4'he : r_nibble <= 7'b1111001;
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4'hf : r_nibble <= 7'b1110001;
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endcase
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end
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TWO : begin
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next <= THREE;
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r_an <= 4'b0010;
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case (in[7:4])
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4'h0 : r_nibble <= 7'b0111111;
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4'h1 : r_nibble <= 7'b0000110;
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4'h2 : r_nibble <= 7'b1011011;
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4'h3 : r_nibble <= 7'b1001111;
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4'h4 : r_nibble <= 7'b1100110;
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4'h5 : r_nibble <= 7'b1101101;
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4'h6 : r_nibble <= 7'b1111101;
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4'h7 : r_nibble <= 7'b0000111;
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4'h8 : r_nibble <= 7'b1111111;
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4'h9 : r_nibble <= 7'b1101111;
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4'ha : r_nibble <= 7'b1110111;
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4'hb : r_nibble <= 7'b1111100;
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4'hc : r_nibble <= 7'b0111001;
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4'hd : r_nibble <= 7'b1011110;
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4'he : r_nibble <= 7'b1111001;
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4'hf : r_nibble <= 7'b1110001;
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endcase
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end
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THREE : begin
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next <= FOUR;
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r_an <= 4'b0100;
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case (in[11:8])
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4'h0 : r_nibble <= 7'b0111111;
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4'h1 : r_nibble <= 7'b0000110;
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4'h2 : r_nibble <= 7'b1011011;
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4'h3 : r_nibble <= 7'b1001111;
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4'h4 : r_nibble <= 7'b1100110;
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4'h5 : r_nibble <= 7'b1101101;
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4'h6 : r_nibble <= 7'b1111101;
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4'h7 : r_nibble <= 7'b0000111;
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4'h8 : r_nibble <= 7'b1111111;
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4'h9 : r_nibble <= 7'b1101111;
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4'ha : r_nibble <= 7'b1110111;
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4'hb : r_nibble <= 7'b1111100;
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4'hc : r_nibble <= 7'b0111001;
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4'hd : r_nibble <= 7'b1011110;
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4'he : r_nibble <= 7'b1111001;
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4'hf : r_nibble <= 7'b1110001;
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endcase
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end
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FOUR : begin
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next <= ONE;
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r_an <= 4'b1000;
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case (in[15:12])
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4'h0 : r_nibble <= 7'b0111111;
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4'h1 : r_nibble <= 7'b0000110;
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4'h2 : r_nibble <= 7'b1011011;
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4'h3 : r_nibble <= 7'b1001111;
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4'h4 : r_nibble <= 7'b1100110;
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4'h5 : r_nibble <= 7'b1101101;
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4'h6 : r_nibble <= 7'b1111101;
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4'h7 : r_nibble <= 7'b0000111;
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4'h8 : r_nibble <= 7'b1111111;
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4'h9 : r_nibble <= 7'b1101111;
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4'ha : r_nibble <= 7'b1110111;
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4'hb : r_nibble <= 7'b1111100;
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4'hc : r_nibble <= 7'b0111001;
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4'hd : r_nibble <= 7'b1011110;
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4'he : r_nibble <= 7'b1111001;
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4'hf : r_nibble <= 7'b1110001;
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endcase
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end
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endcase
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end
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assign seg = ~r_nibble; // inverse active LOW
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assign dp = 1'b1; //dot
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assign an = ~r_an; // inverse active LOW
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endmodule |