76 lines
1.0 KiB
VHDL
76 lines
1.0 KiB
VHDL
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-- Author
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-- Date
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-- Project name
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-- Module name
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--
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-- Detailed module description
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--
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--
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--
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--
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--
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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--Libraries
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--define entity (module) connections to "outside"
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entity ps01q is
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port
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(
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a : in std_Logic;
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b : in std_logic;
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c : in std_logic;
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y1 : out std_logic;
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y2 : out std_logic
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);
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end ps01q;
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--define inside of the module (internal signals, components and architecture)
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architecture behavioral of ps01q is
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--define inside use signals
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signal SIG_INTERNAL : std_logic;
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begin -- jums jaalabo tikai taalaakais.
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--gate one
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SIG_INTERNAL <= A and B;
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--gate two
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Y2 <= C and SIG_INTERNAL;
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--gate three
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Y1 <= A and B;
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--logic gate izsauksanas keywordi:
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-- not
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-- and, nand,
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-- or, xor, nor, xnor
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end behavioral;
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