135 lines
2.4 KiB
Verilog
135 lines
2.4 KiB
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - Testbench fot top module of counter
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//
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// Detailed module description:
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//
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// Top module test bench
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//
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// Code:
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// iverilog -o output.vvp top_tb.v && vvp output.vvp
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// gtkwave -f wave.vcd
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clock_divider.v"
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`include "7segment.v"
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`include "debounce_switch.v"
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`include "counter.v"
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`include "sr_latch.v"
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`include "flip_flop.v"
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//top module
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`include "top.v"
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module top_tb();
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reg clk = 1'b0;
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reg reset = 1'b0;
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reg [3:0] sw = 4'b0001;
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reg start = 1'b1;
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reg up = 1'b0;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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top Test_Unit(
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.clk(clk),
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.sw(sw),
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.btnU(up),
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.btnD(),
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.btnL(start),
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.btnC(reset)
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);
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initial begin
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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start = 1'b0;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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#1_000_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |