imants/RTR532
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
532a2478500a4f1d59098f2f617cd113ab1f5544
RTR532/ld3/dds_vhdl
T
History
Imants Pulkstenis 532a247850 minor changes
2020-06-10 21:39:10 +03:00
..
fir
FIR and IIR filter and test benches are now working
2020-06-10 18:29:47 +03:00
fir_sim
FIR and IIR filter and test benches are now working
2020-06-10 18:29:47 +03:00
fir_import_coef.txt
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir_sim.f
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.bsf
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.cmp
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.qip
FIR and IIR filter and test benches are now working
2020-06-10 18:29:47 +03:00
fir.sip
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.spd
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.vhd
FIR and IIR filter and test benches are now working
2020-06-10 18:29:47 +03:00
IIR.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
lab3_tb.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
lab3.vhd
minor changes
2020-06-10 21:39:10 +03:00
sin_gen_sum_tb.vhd
minor changes
2020-06-10 21:39:10 +03:00
sin_gen_sum.vhd
minor changes
2020-06-10 21:39:10 +03:00
sin_gen_tb.vhd
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qpf
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qsf
minor changes
2020-06-10 21:39:10 +03:00
sin_gen.qws
minor changes
2020-06-10 21:39:10 +03:00
sin_gen.vhd
minor changes
2020-06-10 21:39:10 +03:00