82 lines
1.4 KiB
Verilog
82 lines
1.4 KiB
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 16.02.2020
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// Project name - PS02
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// Module name - Test bench for PS02 project Top module
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//
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// Detailed module description:
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//
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// This module generete clk signal for
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// for tom podule of ps02 project
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// The test is executed using Icarus Verilog!
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//
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// The result can be evaluated in GTKwave application.
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// Code:
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// iverilog -o output.vvp ps02_tb.v && vvp output.vvp
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// gtkwave -f wave.vcd
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//
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// Revision:
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// A - initial design
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//
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//
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/////////////////////////////
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//sub modules
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`include "alu.v"
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`include "ps02_siggen.v"
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//top module
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`include "ps02.v"
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//define module and connections to outside
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module ps02_tb ();
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//define inside use signals
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reg clk = 1'b0;
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reg rst = 1'b0;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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ps02 #(
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.data_width(32)
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) unit_under_test (
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.clk(clk),
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.rst(rst),
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.R(),
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.flag()
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);
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//---------Test--------------------
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initial
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begin
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rst = 1;
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#10;
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rst = 0;
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#100
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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endmodule
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