161 lines
6.5 KiB
VHDL
161 lines
6.5 KiB
VHDL
----------------------------------------------------------------
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-- Author - Imants Pulkstenis
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-- Date - 23.02.2020
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-- Project name - PS03
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-- Module name - Smart traffic light controler
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--
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-- Detailed module description:
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--
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-- Task is to develop a Smart Traffic Light Controller VHDL
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-- module using finite state machine principle (FSM).
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--
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-- Port description
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-- | Port name | Direction | Description |
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-- |------------|------------|--------------------------------------------------------------------------------------------------------------------------|
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-- | Clk | In | 1 GHz clock (1 ns period) |
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-- | Rst | In | Active low reset |
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-- | MR_cars | In | An 8-bit input signal indicating the number of waiting cars at the secondary road traffic light. Interpret as unsigned. |
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-- | MR_ctl | Out | Main road traffic light controlling signal |
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-- | SR_ctl | Out | Secondary road traffic light controlling signal |
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-- Output light mapping for MR_ctl and SR_ctl signals to be used
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-- | Value (2bit binary) | Light output |
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-- |----------------------|-----------------------------------|
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-- | 00 | No light – traffic light is dark |
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-- | 01 | Red light |
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-- | 10 | Yellow light |
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-- | 11 | Green light |
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--
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-- When rst is low, outputs should be dark, no light visible
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-- When rst is high then:
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-- Minimum main road green period length should be at least 30 nanoseconds. When green period ends:
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-- If there are zero cars waiting on the secondary road, then main road starts the green state again
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-- If there are less than PARAMETER cars waiting on the secondary road, green period length is extended
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-- by 30 nanoseconds and then switches to red (and secondary to green)
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-- If there are equals/more than PARAMETER cars waiting on the secondary road, main road switches to red (and secondary to green)
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-- Secondary road green period length is 10 nanoseconds, after that, main road switches to green (and secondary to red)
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-- Each transition (red to green and green to red) should go through 3 nanoseconds yellow light. Yellow lights can happen at the same
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-- time in both traffic directions.
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-- MR_ctl and SR_ctl both must not be green at the same time to avoid traffic accidents.
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-- PARAMETER = 45.
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--
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-- Revision:
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-- A - initial design
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-- B -
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-- C -
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--
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------------------------------------------------------------------
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-- define libraries to be used [part 2 of the VHDL file]
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--Entity declaration [part 3 of the VHDL file].
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entity traffic_light_controller is
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generic
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(
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PARAMETER : integer := 45
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);
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port
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(
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clk : in std_logic;
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rst : in std_Logic;
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MR_cars : in std_logic_vector(7 downto 0);
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MR_ctl : out std_logic_vector(2 downto 0);
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SR_ctl : out std_logic_vector(2 downto 0)
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);
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end smart_tl_ctl;
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--define inside of the module
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architecture behavioral of alu is
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--define inside use signals and components [part 4 of the VHDL file]
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signal state : std_logic_vector(2 downto 0) := "000"; --2b state
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signal cnt : std_logic_vector(7 downto 0) := x"00"; --8b counter
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begin
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--define the operation of the module! [part 5 of the VHDL file]
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '0' then
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state <= "000";
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cnt <= x"00";
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else
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case state is
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when "000" => -- lights off secs
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cnt <= 0;
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state <= "001";
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MR_ctl <= "00";
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SR_ctl <= "00";
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when "001" => -- MR green light 30 ns
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MR_ctl <= "11";
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SR_ctl <= "01";
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if cnt >= 30 then
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if MR_cars == 0 then
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cnt <= 0;
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state <= "001";
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else if MR_cars < PARAMETER then
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cnt <= 0;
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state <= "010";
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else
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cnt <= 0;
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state <= "011";
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end if;
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end if;
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else
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cnt <= cnt + 1;
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state <= "001";
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end if;
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when "010" => -- MR green light 30 ns
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MR_ctl <= "11";
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SR_ctl <= "01";
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if cnt < 30 then
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cnt <= cnt + 1;
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state <= "010";
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else
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cnt <= 0;
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state <= "011";
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end if;
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when "011" => -- MR yellow light 3 ns
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MR_ctl <= "10";
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SR_ctl <= "10";
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if cnt < 3 then
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cnt <= cnt + 1;
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state <= "011";
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else
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cnt <= 0;
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state <= "100";
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end if;
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when "100" => -- SR green light 10 ns
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MR_ctl <= "01";
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SR_ctl <= "11";
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if cnt < 10 then
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cnt <= cnt + 1;
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state <= "100";
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else
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cnt <= 0;
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state <= "101";
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end if;
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when "101" => -- SR yellow light 3 ns
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MR_ctl <= "10";
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SR_ctl <= "10";
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if cnt < 3 then
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cnt <= cnt + 1;
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state <= "101";
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else
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cnt <= 0;
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state <= "001";
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end if;
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when others =>
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cnt <= 0;
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state <= "000";
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end case;
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end if;
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end if;
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end process;
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end behavioral; |