99 lines
2.3 KiB
Verilog
99 lines
2.3 KiB
Verilog
// -----------------------------
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// -- Author - Kriss Osmanis
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// -- Date - 2017-02-25; 2019-02-20
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// -- Project name - PS02
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// -- Module name - PS02 signal generator
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// --
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// -- Detailed module description
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// -- generates values for A, B, op
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// --
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// --
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// -- Revision:
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// -- A - initial design
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// -- B - modified op seq
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// -- C - converted to Verilog code
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// -----------------------------
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//define connections to outside
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module ps02_siggen #( parameter
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data_width = 32
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)(
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input clk,
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input rst,
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output [data_width - 1:0] A,
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output [data_width - 1:0] B,
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output [3:0] op);
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//define inside of the module
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//define inside use signals
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reg [3:0] op_cnt = 'h0;
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reg [data_width - 1:0] reg_A = 'h0;
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reg [data_width - 1:0] reg_B = 'h0;
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always@* begin
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case(op_cnt)
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4'h0: reg_A <= -'d15; //sub
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4'h1: reg_A <= -'d14; //add
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4'h2: reg_A <= 'h0000DEAD; //nand
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4'h3: reg_A <= 'h0000BEEF; //and
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4'h4: reg_A <= 'h0000ABCD; //or
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4'h5: reg_A <= 'h0000EFAD; //nor
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4'h6: reg_A <= 'h00001279; //xor
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4'h7: reg_A <= 'h00000310; //not a
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4'h8: reg_A <= 'h00003010; //not b
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4'h9: reg_A <= -'d1;//incr B
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4'hA: reg_A <= 'd0;//incr A
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4'hb: reg_A <= 'd0;//sub A
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4'hc: reg_A <= 'd0;//sub B
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4'hd: reg_A <= 'h00000F0F;//sll A
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4'he: reg_A <= 'h00000000;//sll B
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4'hf: reg_A <= 'h00001234;//noop
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endcase
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case(op_cnt)
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4'h0: reg_B <= 'd37; //sub
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4'h1: reg_B <= -'d999; //add
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4'h2: reg_B <= 'h00001221; //nand
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4'h3: reg_B <= 'h00000FF0; //and
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4'h4: reg_B <= 'h0000F00F; //or
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4'h5: reg_B <= 'h00008754; //nor
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4'h6: reg_B <= 'h0000ADBF; //xor
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4'h7: reg_B <= 'h0000FECD; //not a
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4'h8: reg_B <= 'h0000CCDC; //not b
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4'h9: reg_B <= 'd0;//incr B
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4'ha: reg_B <= -'d1;//incr A
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4'hb: reg_B <= 'd0;//sub A
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4'hc: reg_B <= 'd0;//sub B
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4'hd: reg_B <= 'h0000F0F0;//sll A
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4'he: reg_B <= 'h0000ABAB;//sll B
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4'hf: reg_B <= 'h00004321; //noop
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endcase
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end
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//define the operation of the module!
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assign A = reg_A;
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assign B = reg_B;
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assign op = op_cnt;
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always@(posedge clk)
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begin
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if (rst == 1)
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op_cnt <= 'b0; //zero counter on rst
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else
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op_cnt <= op_cnt + 1;
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end
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endmodule
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