172 lines
6.6 KiB
Verilog
172 lines
6.6 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 23.02.2020
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// Project name - PS03
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// Module name - Smart traffic light controler
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//
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// Detailed module description:
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//
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// Task is to develop a Smart Traffic Light Controller VHDL(Verilog)
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// module using finite state machine principle (FSM).
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//
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// Port description
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// | Port name | Direction | Description |
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// |------------|------------|--------------------------------------------------------------------------------------------------------------------------|
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// | Clk | In | 1 GHz clock (1 ns period) |
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// | Rst | In | Active low reset |
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// | MR_cars | In | An 8-bit input signal indicating the number of waiting cars at the secondary road traffic light. Interpret as unsigned. |
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// | MR_ctl | Out | Main road traffic light controlling signal |
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// | SR_ctl | Out | Secondary road traffic light controlling signal |
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// Output light mapping for MR_ctl and SR_ctl signals to be used
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// | Value (2bit binary) | Light output |
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// |----------------------|-----------------------------------|
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// | 00 | No light – traffic light is dark |
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// | 01 | Red light |
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// | 10 | Yellow light |
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// | 11 | Green light |
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//
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// When rst is low, outputs should be dark, no light visible
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// When rst is high then:
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// Minimum main road green period length should be at least 30 nanoseconds. When green period ends:
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// If there are zero cars waiting on the secondary road, then main road starts the green state again
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// If there are less than PARAMETER cars waiting on the secondary road, green period length is extended
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// by 30 nanoseconds and then switches to red (and secondary to green)
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// If there are equals/more than PARAMETER cars waiting on the secondary road, main road switches to red (and secondary to green)
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// Secondary road green period length is 10 nanoseconds, after that, main road switches to green (and secondary to red)
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// Each transition (red to green and green to red) should go through 3 nanoseconds yellow light. Yellow lights can happen at the same
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// time in both traffic directions.
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// MR_ctl and SR_ctl both must not be green at the same time to avoid traffic accidents.
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// PARAMETER = 45.
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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module traffic_light_controller #( parameter
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PARAMETER = 45,
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MR_GREEN_TIME = 30-1,
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SR_GREEN_TIME = 10-1,
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YELLOW_TIME = 3-1
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)(
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input clk,
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input rst,
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input [7:0] MR_cars,
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output [1:0] MR_ctl,
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output [1:0] SR_ctl);
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//-------------Internal Constants---------------------------
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localparam [2:0] IDLE = 'h0,
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MR_GREEN_1 = 'h1,
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MR_GREEN_2 = 'h2,
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MR_YELLOW = 'h3,
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SR_GREEN = 'h4,
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SR_YELLOW = 'h5;
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//-------------Internal signals and components--------------
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reg [2:0] r_state = IDLE;
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reg [4:0] r_cnt = 'b0;
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reg [1:0] r_MR_ctl = 'b0,
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r_SR_ctl = 'b0;
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//------------ assignning combionational logic--------------
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assign MR_ctl = r_MR_ctl;
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assign SR_ctl = r_SR_ctl;
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//----next state & outputs, combinational always block------
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always@(posedge clk) begin
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if (rst) begin
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case(r_state)
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IDLE: begin
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r_MR_ctl <= 'b00;
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r_SR_ctl <= 'b00;
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r_state <= MR_GREEN_1;
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r_cnt <= 'd0;
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end
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MR_GREEN_1: begin
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r_MR_ctl <= 'b11;
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r_SR_ctl <= 'b01;
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if (r_cnt >= MR_GREEN_TIME) begin
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if (MR_cars == 0) begin
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r_cnt <= 0;
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r_state <= MR_GREEN_1;
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end
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else if (MR_cars < PARAMETER) begin
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r_cnt <= 0;
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r_state <= MR_GREEN_2;
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end
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else if (MR_cars >= PARAMETER) begin
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r_cnt <= 0;
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r_state <= MR_YELLOW;
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end
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end
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else begin
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r_state <= MR_GREEN_1;
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r_cnt <= r_cnt + 1;
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end
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end
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MR_GREEN_2: begin
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r_MR_ctl <= 'b11;
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r_SR_ctl <= 'b01;
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if (r_cnt >= MR_GREEN_TIME) begin
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r_cnt <= 0;
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r_state <= MR_YELLOW;
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end
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else begin
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r_cnt <= r_cnt + 1;
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r_state <= MR_GREEN_2;
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end
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end
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MR_YELLOW: begin
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r_MR_ctl <= 'b10;
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r_SR_ctl <= 'b10;
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if (r_cnt >= YELLOW_TIME) begin
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r_cnt <= 0;
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r_state <= SR_GREEN;
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end
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else begin
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r_cnt <= r_cnt + 1;
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r_state <= MR_YELLOW;
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end
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end
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SR_GREEN: begin
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r_MR_ctl <= 'b01;
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r_SR_ctl <= 'b11;
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if (r_cnt >= SR_GREEN_TIME) begin
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r_cnt <= 0;
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r_state <= SR_YELLOW;
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end
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else begin
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r_cnt <= r_cnt + 1;
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r_state <= SR_GREEN;
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end
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end
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SR_YELLOW: begin
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r_MR_ctl <= 'b10;
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r_SR_ctl <= 'b10;
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if (r_cnt >= YELLOW_TIME) begin
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r_cnt = 0;
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r_state <= MR_GREEN_1;
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end
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else begin
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r_cnt <= r_cnt + 1;
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r_state <= SR_YELLOW;
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end
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end
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default: r_state <= IDLE; // on error
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endcase
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end
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else begin
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r_state <= IDLE;
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r_MR_ctl <= 'b00;
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r_SR_ctl <= 'b00;
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r_cnt <= 0;
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end
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end
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endmodule |