122 lines
2.4 KiB
Verilog
122 lines
2.4 KiB
Verilog
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - Top module for counter
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//
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// Detailed module description:
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//
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// This module count and displays result on
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// 7-segment display and LEDs
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//
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//
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//
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// Revision:
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// A - initial design
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// B - Correct timmers and 7-segment display.
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// Added UP/DOWN and START/STOP function
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//
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//
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/////////////////////////////
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module top (
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input clk,
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output [15:0] led,
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// 7 segment
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output [6:0] seg,
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output [3:0] an,
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output dp,
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input [3:0] sw,
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input btnC, // reset
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input btnU, // UP counting
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input btnD, // DOWN counting
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input btnL // start/stop
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);
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//------internal wires and registers--------
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wire clk16Hz, clk1kHz,
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w_reset, w_up,
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w_down, w_direction,
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w_start, w_enable;
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wire [15:0] w_counter;
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//------assign outputs----------------------
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assign led = w_counter;
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//-----sub modules--------------------------
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counter counter(
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.clk(clk16Hz),
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.reset(w_reset),
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.direction(w_direction),
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.enable(w_enable),
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.max(sw),
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.counter(w_counter)
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);
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clock_divider #(
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.DIVIDER(50_000), // 50000 * 10ns = 500us
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.WIDTH(24)
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) clock_1kHz_gen (
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.clk(clk),
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.clk_out(clk1kHz)
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);
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clock_divider #(
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.DIVIDER(3_125_000), // 3125000 * 10ns = 31.25ms
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.WIDTH(24)
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) clock_16Hz_gen (
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.clk(clk),
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.clk_out(clk16Hz)
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);
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debounce_switch debounce_switch_reset(
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.clk(clk),
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.i_switch(btnC),
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.o_switch(w_reset)
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);
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debounce_switch debounce_up(
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.clk(clk),
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.i_switch(btnU),
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.o_switch(w_up)
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);
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debounce_switch debounce_down(
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.clk(clk),
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.i_switch(btnD),
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.o_switch(w_down)
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);
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debounce_switch debounce_start(
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.clk(clk),
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.i_switch(btnL),
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.o_switch(w_start)
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);
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sr_latch up_down_latch(
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.clk(clk),
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.up(~w_up),
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.down(~w_down),
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.out(w_direction)
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);
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flip_flop start_stop_flipflop(
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.start(w_start),
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.out(w_enable)
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);
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bin_7segment bin_7segment(
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.clk(clk1kHz), // clock working with 10kHz
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.in(w_counter), // input
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.seg(seg), // individual segments of number
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.an(an), // anode to select character
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.dp(dp) // dot on 7segment display
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);
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//-------------------------------------------------
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endmodule |