diff --git a/ld2/7segment.v b/ld2/7segment.v
new file mode 100644
index 0000000..6ec333a
--- /dev/null
+++ b/ld2/7segment.v
@@ -0,0 +1,151 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - bin_7segment module for counter
+//
+// Detailed module description:
+//
+// This module 16bit input transforms 
+// in 7-segment display induvidual segments
+// as outputs. Input clock is 10kHz and it 
+// drives common anode for 7-segment display
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+module bin_7segment(
+    input           clk,  // clock working with 10kHz
+    input   [15:0]  in,   // input
+    output  [6:0]   seg,  // individual segments of number
+    output  [3:0]   an,   // anode to select character
+    output          dp    // dot on 7segment display
+    );
+
+//-------------Internal Constants---------------------------
+parameter SIZE = 2;
+parameter [SIZE-1:0]    ONE     = 2'b00,
+                        TWO     = 2'b01,
+                        THREE   = 2'b10,
+                        FOUR    = 2'b11;
+
+reg [SIZE-1:0] state=ONE, next=TWO;
+reg [3:0] nibble = 'b0 ;
+
+//---------State register sequential always block-----------
+always @(posedge clk ) begin
+    state <= next;
+end
+//----Next state & outputs, combinational always block------
+
+always@(posedge clk)begin
+  case(state)
+    ONE : begin 
+        next <= TWO;
+        nibble <= in[3:0]; 
+    end
+    TWO : begin
+        next <= THREE;
+        nibble <= in[7:4];
+    end
+    THREE : begin 
+        next <= FOUR;
+        nibble <= in[11:8];
+    end
+    FOUR : begin 
+        next <= ONE;
+        nibble <= in[15:12];
+    end
+  endcase
+end
+
+  assign seg[6] = ( nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[5] = ( nibble == 4'h0 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[4] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF ) ? 1'b0 : 1'b1;
+  assign seg[3] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hB ||
+                    nibble == 4'hC ||
+                    nibble == 4'hD ||
+                    nibble == 4'hE ) ? 1'b0 : 1'b1;
+  assign seg[2] = ( nibble == 4'h0 ||
+                    nibble == 4'h1 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hB ||
+                    nibble == 4'hD ) ? 1'b0 : 1'b1;
+  assign seg[1] = ( nibble == 4'h0 ||
+                    nibble == 4'h1 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h4 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hD ) ? 1'b0 : 1'b1;
+  assign seg[0] = ( nibble == 4'h0 ||
+                    nibble == 4'h2 ||
+                    nibble == 4'h3 ||
+                    nibble == 4'h5 ||
+                    nibble == 4'h6 ||
+                    nibble == 4'h7 ||
+                    nibble == 4'h8 ||
+                    nibble == 4'h9 ||
+                    nibble == 4'hA ||
+                    nibble == 4'hC ||
+                    nibble == 4'hE ||
+                    nibble == 4'hF) ? 1'b0 : 1'b1;
+  assign dp = 1'b1;     //dot
+
+  assign an[0] = (state==ONE)   ? 1'b0 : 1'b1;   
+  assign an[1] = (state==TWO)   ? 1'b0 : 1'b1;
+  assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
+  assign an[3] = (state==FOUR)  ? 1'b0 : 1'b1;
+  
+endmodule
\ No newline at end of file
diff --git a/ld2/7segment_tb.v b/ld2/7segment_tb.v
new file mode 100644
index 0000000..0f83817
--- /dev/null
+++ b/ld2/7segment_tb.v
@@ -0,0 +1,60 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - Testbench for 7-segment module
+//
+// Detailed module description:
+//
+// This module inputs slowly incrementing 
+// numbers in 7-segment module
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+`include "7segment.v"
+
+module bin_7segment_tb();
+
+reg           clk   = 1'b0;
+reg   [15:0]  in    = 'b0;
+wire  [6:0]   seg;
+wire  [3:0]   an;
+wire          dp;
+
+always #1 clk <= ~clk; 
+
+always #40 in <= in + 1;
+
+  initial
+  begin
+    #1000;
+    $finish();
+  end
+    
+  initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+    $display("----------------------------------------------");
+    $display(" ");
+  end
+
+bin_7segment test_unit1(
+    .clk(clk),
+    .in(in),
+    .seg(seg),
+    .an(an),
+    .dp(dp)
+);
+
+
+
+endmodule
\ No newline at end of file
diff --git a/ld2/Basys3_Master.xdc b/ld2/Basys3_Master.xdc
new file mode 100644
index 0000000..03104ae
--- /dev/null
+++ b/ld2/Basys3_Master.xdc
@@ -0,0 +1,299 @@
+## This file is a general .xdc for the Basys3 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## CFGBVS
+set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+## Clock signal
+set_property PACKAGE_PIN W5 [get_ports clk]							
+	set_property IOSTANDARD LVCMOS33 [get_ports clk]
+	create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+ 
+## Switches
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+ 
+
+## LEDs
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+set_property PACKAGE_PIN V13 [get_ports {led[8]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+set_property PACKAGE_PIN V3 [get_ports {led[9]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+set_property PACKAGE_PIN W3 [get_ports {led[10]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+set_property PACKAGE_PIN U3 [get_ports {led[11]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+set_property PACKAGE_PIN P3 [get_ports {led[12]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+set_property PACKAGE_PIN N3 [get_ports {led[13]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+set_property PACKAGE_PIN P1 [get_ports {led[14]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+set_property PACKAGE_PIN L1 [get_ports {led[15]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+	
+	
+##7 segment display
+set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+
+set_property PACKAGE_PIN V7 [get_ports dp]							
+	set_property IOSTANDARD LVCMOS33 [get_ports dp]
+
+set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+
+
+##Buttons
+set_property PACKAGE_PIN U18 [get_ports btnC]						
+	set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+#set_property PACKAGE_PIN T18 [get_ports btnU]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
+#set_property PACKAGE_PIN W19 [get_ports btnL]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
+#set_property PACKAGE_PIN T17 [get_ports btnR]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
+#set_property PACKAGE_PIN U17 [get_ports btnD]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
+ 
+
+
+##Pmod Header JA
+##Sch name = JA1
+#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
+##Sch name = JA2
+#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
+##Sch name = JA3
+#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
+##Sch name = JA4
+#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
+##Sch name = JA7
+#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
+##Sch name = JA8
+#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
+##Sch name = JA9
+#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
+##Sch name = JA10
+#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
+
+
+
+##Pmod Header JB
+##Sch name = JB1
+#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
+##Sch name = JB2
+#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
+##Sch name = JB3
+#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
+##Sch name = JB4
+#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
+##Sch name = JB7
+#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
+##Sch name = JB8
+#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
+##Sch name = JB9
+#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
+##Sch name = JB10 
+#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
+ 
+
+
+##Pmod Header JC
+##Sch name = JC1
+#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
+##Sch name = JC2
+#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
+##Sch name = JC3
+#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
+##Sch name = JC4
+#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
+##Sch name = JC7
+#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
+##Sch name = JC8
+#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
+##Sch name = JC9
+#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
+##Sch name = JC10
+#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
+
+
+##Pmod Header JXADC
+##Sch name = XA1_P
+#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
+##Sch name = XA2_P
+#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
+##Sch name = XA3_P
+#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
+##Sch name = XA4_P
+#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
+##Sch name = XA1_N
+#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
+##Sch name = XA2_N
+#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
+##Sch name = XA3_N
+#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
+##Sch name = XA4_N
+#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
+
+
+
+##VGA Connector
+#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+#set_property PACKAGE_PIN P19 [get_ports Hsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+#set_property PACKAGE_PIN R19 [get_ports Vsync]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+
+
+##USB-RS232 Interface
+#set_property PACKAGE_PIN B18 [get_ports RsRx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+#set_property PACKAGE_PIN A18 [get_ports RsTx]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+
+
+##USB HID (PS/2)
+#set_property PACKAGE_PIN C17 [get_ports PS2Clk]						
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
+	#set_property PULLUP true [get_ports PS2Clk]
+#set_property PACKAGE_PIN B17 [get_ports PS2Data]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]	
+	#set_property PULLUP true [get_ports PS2Data]
+
+
+##Quad SPI Flash
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
+##STARTUPE2 primitive.
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]				
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]					
+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
+
diff --git a/ld2/clock_divider_param.v b/ld2/clock_divider_param.v
new file mode 100644
index 0000000..ee66fbf
--- /dev/null
+++ b/ld2/clock_divider_param.v
@@ -0,0 +1,44 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - clock divider module for counter
+//
+// Detailed module description:
+//
+// This module devide FPGA input clock 
+// by DIVIDER. Result is 50% duty cicle 
+// pulses.
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+
+
+module clock_divider #(
+    parameter DIVIDER =2,
+    parameter WIDTH =2
+) (
+    input clk,
+    output clk_out);
+
+reg state=1'b0, next_state=1'b1;
+reg [WIDTH-1:0] counter = DIVIDER-1 ; 
+
+always@(posedge clk)begin
+    state <= next_state;
+    if ( counter == 0) begin
+        next_state <= ~next_state;
+        counter <= DIVIDER-1;
+    end
+    else if (counter >= 0 )
+        counter <= counter - 1;
+end
+
+assign clk_out = state;
+
+endmodule
\ No newline at end of file
diff --git a/ld2/clock_divider_param_tb.v b/ld2/clock_divider_param_tb.v
new file mode 100644
index 0000000..743d5f8
--- /dev/null
+++ b/ld2/clock_divider_param_tb.v
@@ -0,0 +1,59 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - Testbench for clock divider module
+//
+// Detailed module description:
+//
+// This module just provide clock signal
+// to unit under test
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+
+// `timescale [time unit] / [time precision]
+`timescale 10 ps / 1 ps
+
+`include "clock_divider_param.v"
+
+module clock_divider_param_tb ();
+
+reg clk = 1'b0;
+wire enable;
+
+always #1 clk <= ~clk; 
+
+  initial
+  begin
+    #100;
+    $finish();
+  end
+    
+  initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+    $display("----------------------------------------------");
+    $display(" ");
+  end
+
+clock_divider #(
+    .DIVIDER(2),
+    .WIDTH(2)
+  ) test_unit1 (
+    .clk(clk),
+    .enable(enable)
+);
+
+
+
+endmodule
\ No newline at end of file
diff --git a/ld2/counter.v b/ld2/counter.v
new file mode 100644
index 0000000..8a4dfd5
--- /dev/null
+++ b/ld2/counter.v
@@ -0,0 +1,39 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - counter module
+//
+// Detailed module description:
+//
+// This module counts form 0000 to ffff
+// in hex
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+
+module counter  (
+    input               clk,
+    input               reset,
+    output      [15:0]  counter);
+
+always@(posedge clk) begin
+    if (reset == 'b1) begin
+        r_counter <= 'b0;
+        end
+    else begin
+        r_counter <= r_counter + 1;
+        end
+end
+
+
+reg     [15:0]      r_counter = 'b0;
+
+assign counter = r_counter;
+
+endmodule
\ No newline at end of file
diff --git a/ld2/debounce_switch.v b/ld2/debounce_switch.v
new file mode 100644
index 0000000..e0d30a5
--- /dev/null
+++ b/ld2/debounce_switch.v
@@ -0,0 +1,41 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - debounce module module for reset button
+//
+// Detailed module description:
+//
+// This module is for debouncing push button
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+module debounce_switch(
+    input clk,
+    input i_switch,
+    output o_switch);
+
+    parameter c_debounce_limit=1_000_000;// 10ms at 100MHz
+
+reg r_state=1'b0;
+reg [19:0] r_count = 0;
+
+    always@(posedge clk)begin
+        if (i_switch != r_state && r_count < c_debounce_limit)
+            r_count <= r_count +1; //counter
+        else if (r_count == c_debounce_limit)begin
+            r_count <=0;
+            r_state <= i_switch;
+        end
+        else
+            r_count<=0;
+    end
+
+assign o_switch=r_state;
+
+endmodule
\ No newline at end of file
diff --git a/ld2/schematic/basys3_rm.pdf b/ld2/schematic/basys3_rm.pdf
new file mode 100644
index 0000000..d96ec10
Binary files /dev/null and b/ld2/schematic/basys3_rm.pdf differ
diff --git a/ld2/schematic/basys3_sch.pdf b/ld2/schematic/basys3_sch.pdf
new file mode 100644
index 0000000..14f1d89
Binary files /dev/null and b/ld2/schematic/basys3_sch.pdf differ
diff --git a/ld2/top.v b/ld2/top.v
new file mode 100644
index 0000000..1325f9f
--- /dev/null
+++ b/ld2/top.v
@@ -0,0 +1,82 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - Top module for counter
+//
+// Detailed module description:
+//
+// This module count and displays result on 
+// 7-segment display and LEDs
+//
+//
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+
+module top (
+    input           clk,
+    output  [15:0]  led,
+    // 7 segment
+    output  [6:0]   seg, 
+    output  [3:0]   an, 
+    output          dp,  
+    input   [15:0]   sw,
+    input           btnC     // reset
+    );
+
+//------internal wires and registers--------
+ 
+wire  clk16Hz, clk1kHz, w_reset;    
+wire    [15:0]  w_counter;
+
+//------assign outputs----------------------
+assign led = w_counter;
+
+//-----sub modules--------------------------
+
+counter counter(
+    .clk(clk16Hz),
+    .reset(w_reset),
+    .counter(w_counter)
+);
+
+clock_divider #(
+    .DIVIDER(1_000),
+    .WIDTH(24)
+) clock_1kHz_gen (
+    .clk(clk),
+    .clk_out(clk1kHz)
+);
+
+clock_divider #(
+    .DIVIDER(5_000*625),
+    .WIDTH(22)
+) clock_16Hz_gen (
+    .clk(clk),
+    .clk_out(clk16Hz)
+);
+
+
+debounce_switch debounce_switch_reset(
+    .clk(clk),
+    .i_switch(btnC),
+    .o_switch(w_reset)
+);
+
+bin_7segment bin_7segment(
+    .clk(clk1kHz),   // clock working with 10kHz
+    .in(w_counter),        // input
+    .seg(seg),      // individual segments of number
+    .an(an),        // anode to select character
+    .dp(dp)         // dot on 7segment display
+    );
+
+//-------------------------------------------------
+
+
+endmodule
\ No newline at end of file
diff --git a/ld2/top_tb.v b/ld2/top_tb.v
new file mode 100644
index 0000000..a52035f
--- /dev/null
+++ b/ld2/top_tb.v
@@ -0,0 +1,103 @@
+///////////////////////////// 
+// Author - Imants Pulkstenis
+// Date - 24.03.2020
+// Project name - Lab work No2 - Counter
+// Module name - Testbench fot top module of counter
+//
+// Detailed module description:
+//
+// Top module test bench
+//
+// Code:
+//     iverilog -o output.vvp top_tb.v && vvp output.vvp
+//     gtkwave -f wave.vcd
+//
+// Revision:
+// A - initial design
+// B - 
+// 
+//
+/////////////////////////////
+
+// 100MHz clock on Basys3 -> 10ns period
+// 50% duty cycle 5ns HIGH and 5ns LOW
+//`timescale [time unit] / [time precision]
+`timescale 10 ns / 1ns
+
+//sub modules
+`include "clock_divider_param.v"
+`include "7segment.v"
+`include "debounce_switch.v"
+`include "counter.v"
+
+
+//top module
+`include "top.v"
+
+module top_tb#( parameter
+    WAIT = 1,
+    WAIT_WIDTH = 2,
+    SPEED = 2,
+     //memory parameters
+    ADDR_WIDTH = 17, //19, // 
+    DATA_WIDTH = 12, 
+    DEPTH =  307_200//76_800, // 
+)();
+
+reg clk = 1'b0;
+reg reset = 1'b0;
+
+// 50% duty cycle clock
+always #0.5 clk <= ~clk;
+
+
+reg RsRx;
+wire RsTx;
+
+top Test_Unit(
+    .clk(clk),
+    .btnC(reset) 
+);
+
+initial begin
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    #1_000_000;
+    $display("*");
+    $display(" ");
+    $display("Use this command to open timing diagram:");
+    $display("gtkwave -f wave.vcd");
+    $display("----------------------------------------------");
+    $finish();
+end
+
+initial 
+  begin 
+    $display(" ");
+    $display("----------------------------------------------");
+    $display("          Starting Testbench...");
+    $dumpfile("wave.vcd");
+    $dumpvars(0);
+end
+
+endmodule
\ No newline at end of file