add decription

2020-02-16 13:13:02 +02:00
parent e2311d5b73
commit db3eac9c03
1 changed files with 1 additions and 0 deletions
@@ -14,6 +14,7 @@
 // Revision:
 // A - initial design
 // B - VHDL code are replaced with Verilog
+// C - ALU logic defined in module
 //
 /////////////////////////////