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add decription

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Imants Pulkstenis
2020-02-16 13:13:02 +02:00
parent e2311d5b73
commit db3eac9c03
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ps2/ps02q/alu.v
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@@ -14,6 +14,7 @@
// Revision: // Revision:
// A - initial design // A - initial design
// B - VHDL code are replaced with Verilog // B - VHDL code are replaced with Verilog
// C - ALU logic defined in module
// //
///////////////////////////// /////////////////////////////