Merge branch 'master' of https://github.com/Clockfix/RTR532
This commit is contained in:
+3
-3
@@ -24,11 +24,11 @@
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//Entity declaration [part 3 of the Verilog file].
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module alu #( parameter
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data_width = 32
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)
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)(
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input clk,
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input signed [data_width - 1:0] A,
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input signed [data_width - 1:0] B,
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input unsigned [3:0] op,
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input [3:0] op,
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output signed [data_width - 1:0] R,
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output flag);
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@@ -63,7 +63,7 @@ always@(posedge clk) begin
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endcase
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end
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assign R = reg_R(data_width - 1:0);
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assign R = reg_R[data_width - 1:0];
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assign flag = (reg_R[data_width]==1'b1) ? 1'b1 : 1'b0; //optional
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endmodule
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+3
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@@ -53,8 +53,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
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"
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# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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"
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# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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"
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# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
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# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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"
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# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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+1
-1
@@ -34,7 +34,7 @@ module ps02 #( parameter
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//define inside use signals
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wire signed [data_width - 1:0] A;
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wire signed [data_width - 1:0] B;
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wire unsigned [3:0] op;
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wire [3:0] op;
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//component declaration for A, B, op signal generator
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//port map for A, B, op signal generator
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