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Merge branch 'master' of https://github.com/Clockfix/RTR532

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Imants Pulkstenis
2020-02-16 13:26:05 +02:00
parent db3eac9c03 3c38cb75a8
commit c715347ee5
3 changed files with 7 additions and 7 deletions
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ps2/ps02q/alu.v
+3 -3
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@@ -24,11 +24,11 @@
//Entity declaration [part 3 of the Verilog file]. //Entity declaration [part 3 of the Verilog file].
module alu #( parameter module alu #( parameter
data_width = 32 data_width = 32
) )(
input clk, input clk,
input signed [data_width - 1:0] A, input signed [data_width - 1:0] A,
input signed [data_width - 1:0] B, input signed [data_width - 1:0] B,
input unsigned [3:0] op, input [3:0] op,
output signed [data_width - 1:0] R, output signed [data_width - 1:0] R,
output flag); output flag);
@@ -63,7 +63,7 @@ always@(posedge clk) begin
endcase endcase
end end
assign R = reg_R(data_width - 1:0); assign R = reg_R[data_width - 1:0];
assign flag = (reg_R[data_width]==1'b1) ? 1'b1 : 1'b0; //optional assign flag = (reg_R[data_width]==1'b1) ? 1'b1 : 1'b0; //optional
endmodule endmodule
ps2/ps02q/ps02.qsf
+3 -3
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@@ -53,8 +53,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
" "
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top # Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
" "
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
"
# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
# Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # Obsolete assignment in <Version 19.4> "set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
" "
# Obsolete assignment in <Version 19.4> "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
ps2/ps02q/ps02.v
+1 -1
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@@ -34,7 +34,7 @@ module ps02 #( parameter
//define inside use signals //define inside use signals
wire signed [data_width - 1:0] A; wire signed [data_width - 1:0] A;
wire signed [data_width - 1:0] B; wire signed [data_width - 1:0] B;
wire unsigned [3:0] op; wire [3:0] op;
//component declaration for A, B, op signal generator //component declaration for A, B, op signal generator
//port map for A, B, op signal generator //port map for A, B, op signal generator