From bcfcc84975c31be021e2c1ec2b201b6c7275c1d3 Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Wed, 10 Jun 2020 01:30:00 +0300 Subject: [PATCH] Still need to work on FIR, but IIR is working. --- ld3/dds_vhdl/{IIF.vhd => IIR.vhd} | 12 +- ld3/dds_vhdl/lab3.vhd | 193 ++++++++++++++++++++++++++++++ ld3/dds_vhdl/lab3_tb.vhd | 86 +++++++++++++ ld3/dds_vhdl/sin_gen.qsf | 8 +- ld3/dds_vhdl/sin_gen.vhd | 8 +- ld3/dds_vhdl/sin_gen_sum.vhd | 131 ++++++++++---------- 6 files changed, 362 insertions(+), 76 deletions(-) rename ld3/dds_vhdl/{IIF.vhd => IIR.vhd} (98%) create mode 100644 ld3/dds_vhdl/lab3.vhd create mode 100644 ld3/dds_vhdl/lab3_tb.vhd diff --git a/ld3/dds_vhdl/IIF.vhd b/ld3/dds_vhdl/IIR.vhd similarity index 98% rename from ld3/dds_vhdl/IIF.vhd rename to ld3/dds_vhdl/IIR.vhd index 1797f1e..60e23af 100644 --- a/ld3/dds_vhdl/IIF.vhd +++ b/ld3/dds_vhdl/IIR.vhd @@ -1,6 +1,6 @@ -- ------------------------------------------------------------- -- --- File Name: iif_hdl\ld3_fixed_point2\IIF.vhd +-- File Name: iif_hdl\ld3_fixed_point2\IIR.vhd -- Created: 2020-06-09 20:33:43 -- -- Generated by MATLAB 9.3 and HDL Coder 3.11 @@ -29,8 +29,8 @@ -- ------------------------------------------------------------- -- --- Module: IIF --- Source Path: ld3_fixed_point2/IIF +-- Module: IIR +-- Source Path: ld3_fixed_point2/IIR -- Hierarchy Level: 0 -- -- ------------------------------------------------------------- @@ -38,7 +38,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; -ENTITY IIF IS +ENTITY IIR IS PORT( clk : IN std_logic; reset : IN std_logic; clk_enable : IN std_logic; @@ -46,10 +46,10 @@ ENTITY IIF IS ce_out : OUT std_logic; Out1 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 ); -END IIF; +END IIR; -ARCHITECTURE rtl OF IIF IS +ARCHITECTURE rtl OF IIR IS -- Signals SIGNAL enb : std_logic; diff --git a/ld3/dds_vhdl/lab3.vhd b/ld3/dds_vhdl/lab3.vhd new file mode 100644 index 0000000..2bbaf68 --- /dev/null +++ b/ld3/dds_vhdl/lab3.vhd @@ -0,0 +1,193 @@ +----------------------------- +-- Author Imants Pulkstenis +-- Date 09.06.2020 +-- Project name Labwork No3 +-- Module name lab3 +-- +-- Detailed module description +-- Top level module for Lab.No3 +-- The top module contains two signal generator modules, +-- a signal sum module, and two filters. The first filter +-- is generated using Altera Megawizard plugin IP Core, +-- but second, using the Simulink HDL code generator. +-- +-- +-- Revision: +-- A - initial design +-- B - +-- +----------------------------- +library ieee; --always use this library +use ieee.std_logic_1164.all; --always use this library + +use ieee.numeric_std.all; --use this library if arithmetic required + +--define connections to outside +entity lab3 is + generic + ( + phase_width : integer := 9; + data_width : integer := 16; + phase_incr_one : integer := 37; -- 22050/1664 + phase_incr_two : integer := 57; + sampling_f : integer := 4535; -- 100MHz/22050 + clock_cnt_width : integer := 13 + ); + port + ( + clk : in std_logic; --100mhz clock + rst : in std_logic --rst + ); + end lab3; + +--define inside of the module +architecture behavioral of lab3 is + --define inside use signals + signal signal_f_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal signal_f_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal clk_22050 : std_Logic := '0'; + + --define components to use + component sin_gen is + generic + ( + phase_width : integer := 9; + data_width : integer := 16; + sampling_f : integer := 4535; -- 100MHz/22050Hz + clock_cnt_width : integer := 13 + ); + port + ( + clk : in std_logic; --100mhz clock + rst : in std_logic; --rst + phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency" + phase_out : out std_Logic_vector(phase_width - 1 downto 0); + signal_out : out std_Logic_vector(data_width - 1 downto 0); + fs_out : out std_logic --output sampling clock 22050Hz + ); + end component; + + component sin_gen_sum is + generic + ( + phase_width : integer := 9; + data_width : integer := 16 + ); + port + ( + clk : in std_logic; --100mhz clock + --rst : in std_logic; --rst + signal_in_one : in std_Logic_vector(data_width - 1 downto 0); + signal_in_two : in std_Logic_vector(data_width - 1 downto 0); + signal_out : out std_Logic_vector(data_width - 1 downto 0) + ); + end component; + + component IIR is + port( clk : IN std_logic; + reset : IN std_logic; + clk_enable : IN std_logic; + In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 + ce_out : OUT std_logic; + Out1 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 + ); + end component; + + component fir is + port ( + clk : in std_logic := '0'; -- clk.clk + reset_n : in std_logic := '0'; -- rst.reset_n + ast_sink_data : in std_logic_vector(15 downto 0) := (others => '0'); -- avalon_streaming_sink.data + ast_sink_valid : in std_logic := '0'; -- .valid + ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error + ast_source_data : out std_logic_vector(36 downto 0); -- avalon_streaming_source.data + ast_source_valid : out std_logic; -- .valid + ast_source_error : out std_logic_vector(1 downto 0) -- .error + ); + end component; + + + +begin --define the operation of the module! + +sin_gen_one : sin_gen -- first signal generator +generic map +( + phase_width => phase_width, + data_width => data_width, + sampling_f => sampling_f, + clock_cnt_width => clock_cnt_width +) +port map +( + clk => clk, + rst => rst, + phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)), + --phase_out => phase_out, + signal_out => signal_f_one, + fs_out => clk_22050 +); + +sin_gen_two : sin_gen -- second signal generator +generic map +( + phase_width => phase_width, + data_width => data_width, + sampling_f => sampling_f, + clock_cnt_width => clock_cnt_width +) +port map +( + clk => clk, + rst => rst, + phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)), + --phase_out => phase_out, + signal_out => signal_f_two +); + + +sin_gen_sum_one : sin_gen_sum -- signal sumator +generic map +( + phase_width => phase_width, + data_width => data_width +) +port map +( + clk => clk, + --rst => rst, + signal_in_one => signal_f_one, + signal_in_two => signal_f_two, + signal_out => signal_sum +); + +iir_one : IIR -- IIR filter from Simulink +port map +( + clk => clk_22050, + reset => rst, + clk_enable => '1', + In1 => signal_sum--, -- sfix16_En14 + --ce_out =>, + --Out1 => -- sfix16_En14 +); + +fir_one : fir -- FIR filter from Altera Megawizard plugin IP Core +port map +( + clk => clk, -- clk.clk + reset_n => rst, -- rst.reset_n + ast_sink_data => signal_sum,-- avalon_streaming_sink.data + ast_sink_valid => '1', -- .valid + ast_sink_error => "00" -- .error + -- ast_source_data => -- avalon_streaming_source.data + -- ast_source_valid => -- .valid + -- ast_source_error => -- .error +); + + + + + +end behavioral; \ No newline at end of file diff --git a/ld3/dds_vhdl/lab3_tb.vhd b/ld3/dds_vhdl/lab3_tb.vhd new file mode 100644 index 0000000..4fc6dd0 --- /dev/null +++ b/ld3/dds_vhdl/lab3_tb.vhd @@ -0,0 +1,86 @@ +----------------------------- +-- Author Imants Pulkstenis +-- Date 10.06.2020 +-- Project name Labwork No3 +-- Module name lab3_tb +-- +-- Detailed module description +-- Test bench for top module of lab.No.3 +-- +-- +-- Revision: +-- A - initial design +-- B - +-- +----------------------------- +library ieee; --always use this library +use ieee.std_logic_1164.all; --always use this library + +use ieee.numeric_std.all; --use this library if arithmetic required + +--define connections to outside +entity lab3_tb is + generic + ( + phase_width : integer := 9; + data_width : integer := 16 + ); + end lab3_tb; + +--define inside of the module +architecture behavioral of lab3_tb is + + --signals + signal clk : std_logic := '0'; --100mhz clock + signal rst : std_logic := '0'; --rst + + component lab3 is + generic + ( + phase_width : integer := 9; + data_width : integer := 16 + ); + port + ( + clk : in std_logic; --100mhz clock + rst : in std_logic --rst + ); + end component; + + constant clk_period : time := 10 ns; + + + +begin + + clk <= not clk after clk_period/2; + + + uut : lab3 + generic map + ( + phase_width => phase_width, + data_width => data_width + ) + port map + ( + clk => clk, + rst => rst + ); + + --tb process + process + begin + rst <= '1'; + wait for 100 ns; + rst <= '0'; + + -- wait for clk_period/2; + + + wait; + end process; + + + +end behavioral; \ No newline at end of file diff --git a/ld3/dds_vhdl/sin_gen.qsf b/ld3/dds_vhdl/sin_gen.qsf index c54657d..d34f4a3 100644 --- a/ld3/dds_vhdl/sin_gen.qsf +++ b/ld3/dds_vhdl/sin_gen.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC7C7F23C8 -set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum +set_global_assignment -name TOP_LEVEL_ENTITY lab3 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018" set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" @@ -54,10 +54,12 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE lab3_tb.vhd +set_global_assignment -name VHDL_FILE lab3.vhd set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd set_global_assignment -name VHDL_FILE sin_gen_sum.vhd set_global_assignment -name VHDL_FILE sin_gen_tb.vhd set_global_assignment -name VHDL_FILE sin_gen.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name QIP_FILE fir.qip -set_global_assignment -name SIP_FILE fir.sip \ No newline at end of file +set_global_assignment -name SIP_FILE fir.sip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/ld3/dds_vhdl/sin_gen.vhd b/ld3/dds_vhdl/sin_gen.vhd index e153478..d78d4ba 100644 --- a/ld3/dds_vhdl/sin_gen.vhd +++ b/ld3/dds_vhdl/sin_gen.vhd @@ -22,7 +22,7 @@ use ieee.numeric_std.all; --use this library if arithmetic required entity sin_gen is generic ( - phase_width : integer := 9; + phase_width : integer := 9; data_width : integer := 16; sampling_f : integer := 4535; -- 100MHz/22050 clock_cnt_width : integer := 13 @@ -585,9 +585,9 @@ begin --define the operation of the module! else if clock_cnt <= sampling_f then clock_cnt <= unsigned(clock_cnt) + 1; - --if clock_cnt = (sampling_f-1)/2 then - -- clock_out <= not clock_out; - --end if; + if clock_cnt = (sampling_f-1)/2 then + clock_out <= not clock_out; + end if; else phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr); clock_cnt <= (others => '0'); diff --git a/ld3/dds_vhdl/sin_gen_sum.vhd b/ld3/dds_vhdl/sin_gen_sum.vhd index abcd279..4eba60d 100644 --- a/ld3/dds_vhdl/sin_gen_sum.vhd +++ b/ld3/dds_vhdl/sin_gen_sum.vhd @@ -5,13 +5,16 @@ -- Module name - sin_gen_sum -- -- Detailed module description: --- This is top module containing --- signal genrators, FIR and IIR filter +-- This is sum module adding signals from +-- signal genrators +-- and prepare this signal for FIR and IIR filter -- -- Revision: -- A - initial design -- B - add overflow and unferflow check --- +-- C - Remove sin_gen module out of this module +-- add aditional inputs from top module +-- to compensate changes ----------------------------- library ieee; --always use this library use ieee.std_logic_1164.all; --always use this library @@ -22,42 +25,46 @@ use ieee.numeric_std.all; --use this library if arithmetic required entity sin_gen_sum is generic ( - phase_width : integer := 9; - data_width : integer := 16; - phase_incr_one : integer := 37; - phase_incr_two : integer := 57 + phase_width : integer := 9; + data_width : integer := 16--; + --phase_incr_one : integer := 37; + --phase_incr_two : integer := 57 ); port ( - clk : in std_logic; --100mhz clock - rst : in std_logic; --rst - signal_out : out std_Logic_vector(data_width - 1 downto 0) + clk : in std_logic; --100mhz clock + --rst : in std_logic; --rst + signal_in_one : in std_Logic_vector(data_width - 1 downto 0); + signal_in_two : in std_Logic_vector(data_width - 1 downto 0); + signal_out : out std_Logic_vector(data_width - 1 downto 0) ); end sin_gen_sum; --define inside of the module architecture behavioral of sin_gen_sum is --define inside use signals - signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); - signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 17bit word + --signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + --signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0'); + signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word --define components to use - component sin_gen is - generic - ( - phase_width : integer := 9; - data_width : integer := 16 - ); - port - ( - clk : in std_logic; --100mhz clock - rst : in std_logic; --rst - phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency" - --phase_out : out std_Logic_vector(phase_width - 1 downto 0); - signal_out : out std_Logic_vector(data_width - 1 downto 0) - ); - end component; + -- component sin_gen is + -- generic + -- ( + -- phase_width : integer := 9; + -- data_width : integer := 16 + -- ); + -- port + -- ( + -- clk : in std_logic; --100mhz clock + -- rst : in std_logic; --rst + -- --phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency" + -- signal_f_one : out std_Logic_vector(data_width - 1 downto 0); -- + -- signal_f_two : out std_Logic_vector(data_width - 1 downto 0); + -- --phase_out : out std_Logic_vector(phase_width - 1 downto 0); + -- signal_out : out std_Logic_vector(data_width - 1 downto 0) + -- ); + -- end component; begin --define the operation of the module! --signal output @@ -65,55 +72,53 @@ begin --define the operation of the module! signal_out <= std_logic_Vector(signal_summ); -sin_gen_one : sin_gen -generic map -( - phase_width => phase_width, - data_width => data_width -) -port map -( - clk => clk, - rst => rst, - phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)), - --phase_out => phase_out, - signal_out => signal_out_one -); +-- sin_gen_one : sin_gen +-- generic map +-- ( +-- phase_width => phase_width, +-- data_width => data_width +-- ) +-- port map +-- ( +-- clk => clk, +-- rst => rst, +-- phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)), +-- --phase_out => phase_out, +-- signal_out => signal_out_one +-- ); -sin_gen_two : sin_gen -generic map -( - phase_width => phase_width, - data_width => data_width -) -port map -( - clk => clk, - rst => rst, - phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)), - --phase_out => phase_out, - signal_out => signal_out_two -); +-- sin_gen_two : sin_gen +-- generic map +-- ( +-- phase_width => phase_width, +-- data_width => data_width +-- ) +-- port map +-- ( +-- clk => clk, +-- rst => rst, +-- phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)), +-- --phase_out => phase_out, +-- signal_out => signal_out_two +-- ); --adder process(clk) begin if rising_edge(clk) then - if ((std_logic(signal_out_one(data_width-1)) and std_logic(signal_out_two(data_width-1))) = '1' ) and -- check is bouth numbers negative - (signed(signal_out_one) + signed(signal_out_two) > x"0000" ) -- check sum is positive + if ((std_logic(signal_in_one(data_width-1)) and std_logic(signal_in_two(data_width-1))) = '1' ) and -- check is bouth numbers negative + (signed(signal_in_one) + signed(signal_in_two) > x"0000" ) -- check sum is positive then --max negative signal_summ <= x"8000"; --underflow - else if (std_logic(signal_out_one(data_width-1)) nor std_logic(signal_out_two(data_width-1))) = '1' and -- check is bouth numbers positive - (signed(signal_out_one) + signed(signal_out_two) < x"0000" ) -- check sum is negative + else if (std_logic(signal_in_one(data_width-1)) nor std_logic(signal_in_two(data_width-1))) = '1' and -- check is bouth numbers positive + (signed(signal_in_one) + signed(signal_in_two) < x"0000" ) -- check sum is negative then --max positive signal_summ <= x"7fff"; --overflow else - signal_summ <= signed(signal_out_one) + signed(signal_out_two); -- noramal sum + signal_summ <= signed(signal_in_one) + signed(signal_in_two); -- noramal sum end if; end if; end if; end process; - - end behavioral; \ No newline at end of file