diff --git a/README.md b/README.md index e59e8fc..7241c5f 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,9 @@ +# RTR532 + ![GitHub](https://img.shields.io/github/license/clockfix/RTR532?style=plastic) ![GitHub commit activity](https://img.shields.io/github/commit-activity/m/clockfix/RTR532?style=plastic) ![GitHub last commit](https://img.shields.io/github/last-commit/clockfix/RTR532?style=plastic) ![GitHub top language](https://img.shields.io/github/languages/top/clockfix/RTR532?style=plastic) [![made-with-latex](https://img.shields.io/badge/Made%20with-LaTeX-1f425f.svg?style=plastic)](https://www.latex-project.org/) -# RTR532 + Rīgas Tehniskā Universitāte kurss RTR532 19/20 pavasaris diff --git a/ld1/kcmpnd.m b/ld1/kcmpnd.m new file mode 100644 index 0000000..24acc5e --- /dev/null +++ b/ld1/kcmpnd.m @@ -0,0 +1,6 @@ +function Kcmp = kcmpnd(Ain,Str) +% Kompresora pastiprinajuma koeficients +Kcmp = zeros (size(Ain)); +Kcmp(Ain>0)=log10(Str*Ain(Ain>0)+1)./... + Ain(Ain>0)/log10(Str+1); +Kcmp(Ain<=0)=Str/log(Str+1); \ No newline at end of file diff --git a/ld1/ld1.m b/ld1/ld1.m new file mode 100644 index 0000000..4a1828b --- /dev/null +++ b/ld1/ld1.m @@ -0,0 +1,11 @@ +%% % Runas signala komplresors analogajam signalam + +Ain = linspace(0,1); +Ktr = kcmpnd(Ain,600); +figure(1) +plot(Ain,Ktr) + +Ain = linspace(0,1); +Ktr = kcmpnd(Ain,600); +figure(2) +plot(Ain,Ktr.*Ain) \ No newline at end of file diff --git a/ps01q/ps01q.qpf b/ps01q/ps01q.qpf new file mode 100644 index 0000000..c94226a --- /dev/null +++ b/ps01q/ps01q.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 13:30:03 February 12, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "13:30:03 February 12, 2017" + +# Revisions + +PROJECT_REVISION = "ps01q" diff --git a/ps01q/ps01q.qsf b/ps01q/ps01q.qsf new file mode 100644 index 0000000..ae15a29 --- /dev/null +++ b/ps01q/ps01q.qsf @@ -0,0 +1,56 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 13:30:04 February 12, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ps01q_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC7C7F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY ps01q +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:30:04 FEBRUARY 12, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VHDL_FILE ps01q.vhd +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/ps01q/ps01q.vhd b/ps01q/ps01q.vhd new file mode 100644 index 0000000..2021b36 --- /dev/null +++ b/ps01q/ps01q.vhd @@ -0,0 +1,75 @@ +----------------------------- +-- Author +-- Date +-- Project name +-- Module name +-- +-- Detailed module description +-- +-- +-- +-- +-- +-- +-- +-- Revision: +-- A - initial design +-- B - +-- +----------------------------- + +--Libraries +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +--define entity (module) connections to "outside" +entity ps01q is +port +( + a : in std_Logic; + b : in std_logic; + c : in std_logic; + y1 : out std_logic; + y2 : out std_logic +); +end ps01q; + + +--define inside of the module (internal signals, components and architecture) +architecture behavioral of ps01q is + --define inside use signals + signal SIG_INTERNAL : std_logic; + + +begin -- jums jaalabo tikai taalaakais. + + + --gate one + SIG_INTERNAL <= A and B; + + + --gate two + Y2 <= C and SIG_INTERNAL; + + + --gate three + Y1 <= A and B; + + + --logic gate izsauksanas keywordi: + -- not + -- and, nand, + -- or, xor, nor, xnor + + + + + +end behavioral; + + + + +