From 9c73fa1193a83d1566ddd8e687dea658e5be2080 Mon Sep 17 00:00:00 2001
From: Imants Pulkstenis <imants.pulkstenis@gmail.com>
Date: Mon, 13 Apr 2020 19:23:11 +0300
Subject: [PATCH] direction and start stop now working

---
 ld2/counter.v   |  4 ++--
 ld2/flip_flop.v | 24 +++++++++++-------------
 ld2/sr_latch.v  | 22 ++++++++++++++--------
 ld2/top.v       | 31 ++++++++++---------------------
 4 files changed, 37 insertions(+), 44 deletions(-)

diff --git a/ld2/counter.v b/ld2/counter.v
index e9e00c6..06dfa2f 100644
--- a/ld2/counter.v
+++ b/ld2/counter.v
@@ -34,10 +34,10 @@ always@(posedge clk) begin
                 if (r_adder >= max )begin
                     r_adder <= 0;
                     if (direction) begin
-                        r_counter <= r_counter + 1;
+                        r_counter <= r_counter - 1;
                     end
                     else begin
-                        r_counter <= r_counter - 1;
+                        r_counter <= r_counter + 1;
                     end
                 end 
                 else begin
diff --git a/ld2/flip_flop.v b/ld2/flip_flop.v
index eedbaa7..ea078ac 100644
--- a/ld2/flip_flop.v
+++ b/ld2/flip_flop.v
@@ -16,17 +16,15 @@
 /////////////////////////////
 
 module flip_flop (   
-    input clk,
-    input rst,
-    input t,
-    output reg q);
- 
-always @ (posedge clk) begin
-    if (!rst) 
-      q <= 0;
-    else if (t)
-        q <= ~q;
-    else
-        q <= q;
-  end
+    input start,
+    output out);
+
+reg r_out = 1'b0;
+
+always@(posedge start) begin
+    r_out <= ~r_out;
+end
+
+assign out = r_out;
+
 endmodule
\ No newline at end of file
diff --git a/ld2/sr_latch.v b/ld2/sr_latch.v
index 150144d..e319e57 100644
--- a/ld2/sr_latch.v
+++ b/ld2/sr_latch.v
@@ -6,7 +6,7 @@
 //
 // Detailed module description:
 //
-// This is SR latch for swoching
+// This is SR latch for swiching
 // between UP or DOWN counting
 //
 // Revision:
@@ -16,13 +16,19 @@
 //
 /////////////////////////////
 module sr_latch(
-        input wire S, R, C,
-        output reg Q, notQ
+        input wire clk, up, down,
+        output wire out
     );
 
-always@(S, R, C, Q, notQ)
-    if(C) begin
-        Q <= (~R & Q) | S;
-        Q <= (~S & Q) | R;
-    end
+reg r_out = 1'b0;
+
+always@(posedge clk) begin
+    case ({up,down})
+        2'b01 :  r_out <= 0;
+        2'b10 :  r_out <= 1;
+        default : r_out <= r_out;
+    endcase
+end
+assign out = r_out;
+
 endmodule
diff --git a/ld2/top.v b/ld2/top.v
index 98abbe5..d41b7e3 100644
--- a/ld2/top.v
+++ b/ld2/top.v
@@ -51,7 +51,7 @@ counter counter(
     .clk(clk16Hz),
     .reset(w_reset),
     .direction(w_direction),
-    .enable(1'b1),
+    .enable(w_enable),
     .max(sw),
     .counter(w_counter)
 );
@@ -96,28 +96,17 @@ debounce_switch debounce_start(
     .o_switch(w_start)
 );
 
-// flip_flop flip_flop(
-//     .clk(clk),
-//     .rst(1'b1),
-//     .t(w_start),
-//     .q(w_enable)
-// );
-
-sr_latch sr_latch(
-    .C(clk),
-    .S(~w_up),
-    .R(~w_down),
-    .Q(w_direction),
-    .notQ()
+sr_latch up_down_latch(
+    .clk(clk),
+    .up(~w_up),
+    .down(~w_down),
+    .out(w_direction)
 );
 
-// sr_latch start_latch(
-//     .C(clk),
-//     .S(~w_start),
-//     .R(~w_start&w_enable),
-//     .Q(w_enable),
-//     .notQ()
-// );
+flip_flop start_stop_flipflop(
+    .start(w_start),
+    .out(w_enable)
+);
 
 bin_7segment bin_7segment(
     .clk(clk1kHz),  // clock working with 10kHz