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remove overflow flag

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This commit is contained in:
Imants Pulkstenis
2020-02-16 18:36:07 +02:00
parent 818b11e338
commit 6d158867bb
4 changed files with 152 additions and 124 deletions
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ps2/ps02q/alu.v
+23 -79
View File
@@ -36,91 +36,35 @@ module alu #( parameter
//define inside of the module
//define inside use signals and components [part 4 of the VHDL file]
reg [data_width :0] reg_R = 'h0; // width is 33 to capture overflow or underflow
reg reg_flag = 'b0;
reg [data_width - 2 : 0 ] reg_max_pos = 'b1; // maximum
reg [data_width -1 :0] reg_R = 'h0;
//define the operation of the module! [part 5 of the VHDL file]
always@(posedge clk) begin
case (op)
4'h0: begin
reg_R <= A - B;
if ( B > A ) begin
reg_flag <= 'b1;
end
else reg_flag <= 'b0;
end
4'h1: begin
reg_R <= A + B;
if ((A + B) > reg_max_pos ) begin
reg_flag <= 'b1;
end
else reg_flag <= 'b0;
end
4'h2: begin
reg_R <= ~(A & B);
reg_flag <= 'b0;
end
4'h3: begin
reg_R <= A & B;
reg_flag <= 'b0;
end
4'h4: begin
reg_R <= A | B;
reg_flag <= 'b0;
end
4'h5: begin
reg_R <= ~(A | B);
reg_flag <= 'b0;
end
4'h6: begin
reg_R <= A ^ B;
reg_flag <= 'b0;
end
4'h7: begin
reg_R <= ~A;
reg_flag <= 'b0;
end
4'h8: begin
reg_R <= ~B;
reg_flag <= 'b0;
end
4'h9: begin
reg_R <= B + 1;
if ( B == reg_max_pos ) reg_flag <= 'b1;
end
4'ha: begin
reg_R <= A + 1;
if ( reg_max_pos ) reg_flag <= 'b1;
end
4'hb: begin
reg_R <= A - 1;
if ( A == {1'b1, ~reg_max_pos } ) reg_flag <= 'b1;
end
4'hc: begin
reg_R <= B - 1;
if ( B == {1'b1, ~reg_max_pos } ) reg_flag <= 'b1;
end
4'hd: begin
reg_R <= A << 1; // << Shift Left, Logical (fill with zero)
reg_flag <= 'b0; // <<< Shift Left, Arithmetic (keep sign)
end
4'he: begin
reg_R <= A >> 1; // >> Shift Right, Logical (fill with zero)
reg_flag <= 'b0; // >>> Shift Right, Arithmetic (keep sign)
end
4'hf: begin
reg_R <= 'b0;
reg_flag <= 'b0;
end
default: begin
reg_R <= 'b0;
reg_flag <= 'b0;
end
4'h0: reg_R <= (A - B);
4'h1: reg_R <= (A + B);
4'h2: reg_R[data_width - 1:0] <= (A ~& B);
4'h3: reg_R[data_width - 1:0] <= (A & B);
4'h4: reg_R[data_width - 1:0] <= (A | B);
4'h5: reg_R[data_width - 1:0] <= (A ~| B);
4'h6: reg_R[data_width - 1:0] <= (A ^ B);
4'h7: reg_R[data_width - 1:0] <= ~A;
4'h8: reg_R[data_width - 1:0] <= ~B;
4'h9: reg_R <= B + 1;
4'ha: reg_R <= A + 1;
4'hb: reg_R <= A - 1;
4'hc: reg_R <= B - 1;
4'hd: reg_R[data_width - 1:0] <= A << 1; // << Shift Left, Logical (fill with zero)
// <<< Shift Left, Arithmetic (keep sign)
4'he: reg_R[data_width - 1:0] <= A >> 1; // >> Shift Right, Logical (fill with zero)
// >>> Shift Right, Arithmetic (keep sign)
4'hf: reg_R[data_width - 1:0] <= 'b0;
default: reg_R[data_width - 1:0] <= 'b0;
endcase
end
assign R = reg_R[data_width - 1:0];
assign flag = reg_flag; //optional
assign R = reg_R;
assign flag = 1'b0; //optional
endmodule
ps2/ps02q/ps02.v
+4 -4
View File
@@ -26,15 +26,15 @@ module ps02 #( parameter
)(
input clk,
input rst,
output signed [data_width - 1:0] R,
output [data_width - 1:0] R,
output flag
);
//define inside of the module
//define inside use signals
wire signed [data_width - 1:0] A;
wire signed [data_width - 1:0] B;
wire [3:0] op;
wire [data_width - 1:0] A;
wire [data_width - 1:0] B;
wire [3:0] op;
//component declaration for A, B, op signal generator
//port map for A, B, op signal generator
ps2/ps02q/ps02_siggen.v
+43 -40
View File
@@ -30,53 +30,56 @@ module ps02_siggen #( parameter
//define inside use signals
reg [3:0] op_cnt = 'h0;
reg [data_width - 1:0] reg_A = 'h0;
reg [data_width - 1:0] reg_B = 'h0;
reg [data_width - 1 : 0] A_list [15:0] =
{
-'d15, //sub
-'d14, //add
'h0000DEAD, //nand
'h0000BEEF, //and
'h0000ABCD, //or
'h0000EFAD, //nor
'h00001279, //xor
'h00000310, //not a
'h00003010, //not b
-'d1,//incr B
'd0,//incr A
'd0,//sub A
'd0,//sub B
'h00000F0F,//sll A
'h00000000,//sll B
'h00001234//noop
};
always@* begin
case(op_cnt)
4'h0: reg_A <= -'d15; //sub
4'h1: reg_A <= -'d14; //add
4'h2: reg_A <= 'h0000DEAD; //nand
4'h3: reg_A <= 'h0000BEEF; //and
4'h4: reg_A <= 'h0000ABCD; //or
4'h5: reg_A <= 'h0000EFAD; //nor
4'h6: reg_A <= 'h00001279; //xor
4'h7: reg_A <= 'h00000310; //not a
4'h8: reg_A <= 'h00003010; //not b
4'h9: reg_A <= -'d1;//incr B
4'hA: reg_A <= 'd0;//incr A
4'hb: reg_A <= 'd0;//sub A
4'hc: reg_A <= 'd0;//sub B
4'hd: reg_A <= 'h00000F0F;//sll A
4'he: reg_A <= 'h00000000;//sll B
4'hf: reg_A <= 'h00001234;//noop
endcase
case(op_cnt)
4'h0: reg_B <= 'd37; //sub
4'h1: reg_B <= -'d999; //add
4'h2: reg_B <= 'h00001221; //nand
4'h3: reg_B <= 'h00000FF0; //and
4'h4: reg_B <= 'h0000F00F; //or
4'h5: reg_B <= 'h00008754; //nor
4'h6: reg_B <= 'h0000ADBF; //xor
4'h7: reg_B <= 'h0000FECD; //not a
4'h8: reg_B <= 'h0000CCDC; //not b
4'h9: reg_B <= 'd0;//incr B
4'ha: reg_B <= -'d1;//incr A
4'hb: reg_B <= 'd0;//sub A
4'hc: reg_B <= 'd0;//sub B
4'hd: reg_B <= 'h0000F0F0;//sll A
4'he: reg_B <= 'h0000ABAB;//sll B
4'hf: reg_B <= 'h00004321; //noop
endcase
reg [data_width - 1 : 0] V_list [15:0] =
{
'd37, //sub
-'d999, //add
'h00001221, //nand
'h00000FF0, //and
'h0000F00F, //or
'h00008754, //nor
'h0000ADBF, //xor
'h0000FECD, //not a
'h0000CCDC, //not b
'd0,//incr B
-'d1,//incr A
'd0,//sub A
'd0,//sub B
'h0000F0F0,//sll A
'h0000ABAB,//sll B
'h00004321 //noop
};
end
//define the operation of the module!
assign A = A_list(op_cnt);
assign B = B_list(op_cnt);
assign A = reg_A;
assign B = reg_B;
assign op = op_cnt;
always@(posedge clk)
begin
ps2/ps02q/ps02_tb.v
+81
View File
@@ -0,0 +1,81 @@
/////////////////////////////
// Author - Imants Pulkstenis
// Date - 16.02.2020
// Project name - PS02
// Module name - Test bench for PS02 project Top module
//
// Detailed module description:
//
// This module generete clk signal for
// for tom podule of ps02 project
// The test is executed using Icarus Verilog!
//
// The result can be evaluated in GTKwave application.
// Code:
// iverilog -o output.vvp ps02_tb.v && vvp output.vvp
// gtkwave -f wave.vcd
//
// Revision:
// A - initial design
//
//
/////////////////////////////
//sub modules
`include "alu.v"
`include "ps02_siggen.v"
//top module
`include "ps02.v"
//define module and connections to outside
module ps02_tb ();
//define inside use signals
reg clk = 1'b0;
reg rst = 1'b0;
//---------Test script----------------
// 50% duty cycle clock
always #0.5 clk <= ~clk;
//-----Unit Under test---------------
ps02 #(
.data_width(32)
) unit_under_test (
.clk(clk),
.rst(rst),
.R(),
.flag()
);
//---------Test--------------------
initial
begin
rst = 1;
#10;
rst = 0;
#100
$finish();
end
initial
begin
$display(" ");
$display("----------------------------------------------");
$display(" Starting Testbench...");
$dumpfile("wave.vcd");
$dumpvars(0);
$display("----------------------------------------------");
$display(" ");
end
endmodule