imants/RTR532
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor changes

Browse Source
This commit is contained in:
Imants Pulkstenis
2020-02-24 00:18:10 +02:00
parent 71b037e9fe
commit 5d5a40afe4
3 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ps3/ps03q/tlc_tb.v
+2 -2
View File
@@ -26,7 +26,7 @@
///////////////////////////////////////////////////////////////////
//UUT module
`include "traffic_light_controler.v"
`include "traffic_light_controller.v"
// 1GHz clock -> 1ns period
// 50% duty cycle 0.5ns HIGH and 0.5ns LOW
@@ -48,7 +48,7 @@ integer ii=0;
always #0.5 clk <= ~clk;
//-----Unit Under test---------------
smart_tl_ctl #(
traffic_light_controller #(
.PARAMETER(45)
) unit_under_test (
.clk(clk),
ps3/ps03q/traffic_light_controller.v
+1 -1
View File
@@ -46,7 +46,7 @@
//
///////////////////////////////////////////////////////////////////
module trafic_light_controller #( parameter
module traffic_light_controller #( parameter
PARAMETER = 45,
MR_GREEN_TIME = 30-1,
SR_GREEN_TIME = 10-1,
ps3/ps03q/traffic_light_controller.vhdl
+1 -1
View File
@@ -52,7 +52,7 @@ use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--Entity declaration [part 3 of the VHDL file].
entity smart_tl_ctl is
entity traffic_light_controller is
generic
(
PARAMETER : integer := 45