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minor changes

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This commit is contained in:
Imants Pulkstenis
2020-06-10 21:39:10 +03:00
parent cdb68967c9
commit 532a247850
22 changed files with 866 additions and 20 deletions
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ld3/dds_vhdl/sin_gen_sum_tb.vhd
+4 -4
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@@ -24,10 +24,10 @@ entity sin_gen_sum_tb is
(
phase_width : integer := 9;
data_width : integer := 16;
phase_incr_one : integer := 37;
phase_incr_one : integer := 37;
phase_incr_two : integer := 57;
sampling_f : integer := 4535; -- 100MHz/22050Hz
clock_cnt_width : integer := 13
clock_cnt_width : integer := 13
);
end sin_gen_sum_tb;
@@ -43,7 +43,7 @@ architecture behavioral of sin_gen_sum_tb is
signal clk : std_logic := '0'; --100mhz clock
signal rst : std_logic := '0'; --rst
signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal clk_22050 : std_Logic := '0';
signal clk_22050 : std_Logic := '0';
--define components to use
component sin_gen_sum is
@@ -69,7 +69,7 @@ architecture behavioral of sin_gen_sum_tb is
data_width : integer := 16;
sampling_f : integer := 4535; -- 100MHz/22050Hz
clock_cnt_width : integer := 13
clock_cnt_width : integer := 13
);
port
(