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minor changes

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This commit is contained in:
Imants Pulkstenis
2020-06-10 21:39:10 +03:00
parent cdb68967c9
commit 532a247850
22 changed files with 866 additions and 20 deletions
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ld3/dds_vhdl/lab3.vhd
+5 -5
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@@ -28,8 +28,8 @@ entity lab3 is
(
phase_width : integer := 9;
data_width : integer := 16;
phase_incr_one : integer := 37; -- Ph_inc = (f_out * 2^(B_n))/f_clk
phase_incr_two : integer := 57; -- 2496 * 2^9 / 22050
phase_incr_one : integer := 37; -- 22050/1664
phase_incr_two : integer := 57;
sampling_f : integer := 4535; -- 100MHz/22050
clock_cnt_width : integer := 13
);
@@ -45,9 +45,9 @@ architecture behavioral of lab3 is
--define inside use signals
signal signal_f_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal signal_f_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal clk_22050 : std_Logic := '0';
signal not_rst : std_Logic := '1';
signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal clk_22050 : std_Logic := '0';
signal not_rst : std_Logic := '1';
--define components to use
component sin_gen is
ld3/dds_vhdl/sin_gen.qsf
+6 -3
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@@ -39,7 +39,7 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY sin_gen_sum
set_global_assignment -name TOP_LEVEL_ENTITY lab3
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
@@ -54,10 +54,13 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE IIR.vhd
set_global_assignment -name VHDL_FILE lab3_tb.vhd
set_global_assignment -name VHDL_FILE lab3.vhd
set_global_assignment -name VHDL_FILE sin_gen_sum_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen_sum.vhd
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name QIP_FILE fir.qip
set_global_assignment -name SIP_FILE fir.sip
set_global_assignment -name SIP_FILE fir.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
ld3/dds_vhdl/sin_gen.qws
BIN
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Binary file not shown.
ld3/dds_vhdl/sin_gen.vhd
+5 -5
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@@ -22,7 +22,7 @@ use ieee.numeric_std.all; --use this library if arithmetic required
entity sin_gen is
generic
(
phase_width : integer := 9;
phase_width : integer := 9;
data_width : integer := 16;
sampling_f : integer := 4535; -- 100MHz/22050
clock_cnt_width : integer := 13
@@ -566,7 +566,7 @@ architecture behavioral of sin_gen is
-- clock divider counter - for generating 22050Hz fs clock
signal clock_cnt : unsigned(clock_cnt_width - 1 downto 0) := (others => '0');
-- clock output
signal clock_out : std_logic := '0';
signal clock_out : std_logic := '1';
begin --define the operation of the module!
@@ -585,9 +585,9 @@ begin --define the operation of the module!
else
if clock_cnt <= sampling_f then
clock_cnt <= unsigned(clock_cnt) + 1;
--if clock_cnt = (sampling_f-1)/2 then
-- clock_out <= not clock_out;
--end if;
if clock_cnt = (sampling_f-1)/2 then
clock_out <= not clock_out;
end if;
else
phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr);
clock_cnt <= (others => '0');
ld3/dds_vhdl/sin_gen_sum.vhd
+56 -3
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@@ -26,7 +26,9 @@ entity sin_gen_sum is
generic
(
phase_width : integer := 9;
data_width : integer := 16
data_width : integer := 16--;
--phase_incr_one : integer := 37;
--phase_incr_two : integer := 57
);
port
(
@@ -40,15 +42,66 @@ entity sin_gen_sum is
--define inside of the module
architecture behavioral of sin_gen_sum is
signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word
--define inside use signals
--signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
--signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal signal_summ : signed(data_width - 1 downto 0) := (others => '0'); -- 16bit word
--define components to use
-- component sin_gen is
-- generic
-- (
-- phase_width : integer := 9;
-- data_width : integer := 16
-- );
-- port
-- (
-- clk : in std_logic; --100mhz clock
-- rst : in std_logic; --rst
-- --phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
-- signal_f_one : out std_Logic_vector(data_width - 1 downto 0); --
-- signal_f_two : out std_Logic_vector(data_width - 1 downto 0);
-- --phase_out : out std_Logic_vector(phase_width - 1 downto 0);
-- signal_out : out std_Logic_vector(data_width - 1 downto 0)
-- );
-- end component;
begin --define the operation of the module!
--signal output
signal_out <= std_logic_Vector(signal_summ);
-- sin_gen_one : sin_gen
-- generic map
-- (
-- phase_width => phase_width,
-- data_width => data_width
-- )
-- port map
-- (
-- clk => clk,
-- rst => rst,
-- phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
-- --phase_out => phase_out,
-- signal_out => signal_out_one
-- );
-- sin_gen_two : sin_gen
-- generic map
-- (
-- phase_width => phase_width,
-- data_width => data_width
-- )
-- port map
-- (
-- clk => clk,
-- rst => rst,
-- phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
-- --phase_out => phase_out,
-- signal_out => signal_out_two
-- );
--adder
process(clk)
begin
ld3/dds_vhdl/sin_gen_sum_tb.vhd
+4 -4
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@@ -24,10 +24,10 @@ entity sin_gen_sum_tb is
(
phase_width : integer := 9;
data_width : integer := 16;
phase_incr_one : integer := 37;
phase_incr_one : integer := 37;
phase_incr_two : integer := 57;
sampling_f : integer := 4535; -- 100MHz/22050Hz
clock_cnt_width : integer := 13
clock_cnt_width : integer := 13
);
end sin_gen_sum_tb;
@@ -43,7 +43,7 @@ architecture behavioral of sin_gen_sum_tb is
signal clk : std_logic := '0'; --100mhz clock
signal rst : std_logic := '0'; --rst
signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
signal clk_22050 : std_Logic := '0';
signal clk_22050 : std_Logic := '0';
--define components to use
component sin_gen_sum is
@@ -69,7 +69,7 @@ architecture behavioral of sin_gen_sum_tb is
data_width : integer := 16;
sampling_f : integer := 4535; -- 100MHz/22050Hz
clock_cnt_width : integer := 13
clock_cnt_width : integer := 13
);
port
(