From 45652812e395635be090caaf2617f3dc4499121c Mon Sep 17 00:00:00 2001 From: Imants Pulkstenis Date: Mon, 13 Apr 2020 00:25:43 +0300 Subject: [PATCH] add aditional modules for start/stop and for up down counter --- ld2/Basys3_Master.xdc | 12 ++++----- ld2/counter.v | 25 +++++++++++++------ ld2/debounce_switch.v | 2 +- ld2/flip_flop.v | 32 ++++++++++++++++++++++++ ld2/sr_latch.v | 28 +++++++++++++++++++++ ld2/top.v | 57 ++++++++++++++++++++++++++++++++++++++++--- ld2/top_tb.v | 25 +++++++++---------- 7 files changed, 149 insertions(+), 32 deletions(-) create mode 100644 ld2/flip_flop.v create mode 100644 ld2/sr_latch.v diff --git a/ld2/Basys3_Master.xdc b/ld2/Basys3_Master.xdc index 29fc92f..b42a594 100644 --- a/ld2/Basys3_Master.xdc +++ b/ld2/Basys3_Master.xdc @@ -114,14 +114,14 @@ set_property PACKAGE_PIN W4 [get_ports {an[3]}] ##Buttons set_property PACKAGE_PIN U18 [get_ports btnC] set_property IOSTANDARD LVCMOS33 [get_ports btnC] -#set_property PACKAGE_PIN T18 [get_ports btnU] - #set_property IOSTANDARD LVCMOS33 [get_ports btnU] -#set_property PACKAGE_PIN W19 [get_ports btnL] - #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +set_property PACKAGE_PIN T18 [get_ports btnU] + set_property IOSTANDARD LVCMOS33 [get_ports btnU] +set_property PACKAGE_PIN W19 [get_ports btnL] + set_property IOSTANDARD LVCMOS33 [get_ports btnL] #set_property PACKAGE_PIN T17 [get_ports btnR] #set_property IOSTANDARD LVCMOS33 [get_ports btnR] -#set_property PACKAGE_PIN U17 [get_ports btnD] - #set_property IOSTANDARD LVCMOS33 [get_ports btnD] +set_property PACKAGE_PIN U17 [get_ports btnD] + set_property IOSTANDARD LVCMOS33 [get_ports btnD] diff --git a/ld2/counter.v b/ld2/counter.v index 48d0eae..e9e00c6 100644 --- a/ld2/counter.v +++ b/ld2/counter.v @@ -20,20 +20,29 @@ module counter ( input clk, input reset, + input enable, + input direction, input [3:0] max, - output [15:0] counter); + output [15:0] counter); always@(posedge clk) begin if (reset == 'b1) begin - r_adder <= 'b0; + r_counter <= 'b0; end else begin - if (r_adder >= max )begin - r_counter <= r_counter + 1; - r_adder <= 0; - end - else begin - r_adder <= r_adder + 1; + if(enable)begin + if (r_adder >= max )begin + r_adder <= 0; + if (direction) begin + r_counter <= r_counter + 1; + end + else begin + r_counter <= r_counter - 1; + end + end + else begin + r_adder <= r_adder + 1; + end end end end diff --git a/ld2/debounce_switch.v b/ld2/debounce_switch.v index e0d30a5..4d0b2dc 100644 --- a/ld2/debounce_switch.v +++ b/ld2/debounce_switch.v @@ -20,7 +20,7 @@ module debounce_switch( input i_switch, output o_switch); - parameter c_debounce_limit=1_000_000;// 10ms at 100MHz + parameter c_debounce_limit=1_000_000;// 10ms@100MHz reg r_state=1'b0; reg [19:0] r_count = 0; diff --git a/ld2/flip_flop.v b/ld2/flip_flop.v new file mode 100644 index 0000000..eedbaa7 --- /dev/null +++ b/ld2/flip_flop.v @@ -0,0 +1,32 @@ +///////////////////////////// +// Author - Imants Pulkstenis +// Date - 24.03.2020 +// Project name - Lab work No2 - Counter +// Module name - SR latch module for counter +// +// Detailed module description: +// +// This is Flip Flop for START/STOP function +// +// Revision: +// A - initial design +// B - +// +// +///////////////////////////// + +module flip_flop ( + input clk, + input rst, + input t, + output reg q); + +always @ (posedge clk) begin + if (!rst) + q <= 0; + else if (t) + q <= ~q; + else + q <= q; + end +endmodule \ No newline at end of file diff --git a/ld2/sr_latch.v b/ld2/sr_latch.v new file mode 100644 index 0000000..150144d --- /dev/null +++ b/ld2/sr_latch.v @@ -0,0 +1,28 @@ +///////////////////////////// +// Author - Imants Pulkstenis +// Date - 24.03.2020 +// Project name - Lab work No2 - Counter +// Module name - SR latch module for counter +// +// Detailed module description: +// +// This is SR latch for swoching +// between UP or DOWN counting +// +// Revision: +// A - initial design +// B - +// +// +///////////////////////////// +module sr_latch( + input wire S, R, C, + output reg Q, notQ + ); + +always@(S, R, C, Q, notQ) + if(C) begin + Q <= (~R & Q) | S; + Q <= (~S & Q) | R; + end +endmodule diff --git a/ld2/top.v b/ld2/top.v index 5f4ef6e..98abbe5 100644 --- a/ld2/top.v +++ b/ld2/top.v @@ -13,7 +13,8 @@ // // Revision: // A - initial design -// B - +// B - Correct timmers and 7-segment display. +// Added UP/DOWN and START/STOP function // // ///////////////////////////// @@ -26,12 +27,18 @@ module top ( output [3:0] an, output dp, input [3:0] sw, - input btnC // reset + input btnC, // reset + input btnU, // UP counting + input btnD, // DOWN counting + input btnL // start/stop ); //------internal wires and registers-------- -wire clk16Hz, clk1kHz, w_reset; +wire clk16Hz, clk1kHz, + w_reset, w_up, + w_down, w_direction, + w_start, w_enable; wire [15:0] w_counter; @@ -43,6 +50,8 @@ assign led = w_counter; counter counter( .clk(clk16Hz), .reset(w_reset), + .direction(w_direction), + .enable(1'b1), .max(sw), .counter(w_counter) ); @@ -63,13 +72,53 @@ clock_divider #( .clk_out(clk16Hz) ); - debounce_switch debounce_switch_reset( .clk(clk), .i_switch(btnC), .o_switch(w_reset) ); +debounce_switch debounce_up( + .clk(clk), + .i_switch(btnU), + .o_switch(w_up) +); + +debounce_switch debounce_down( + .clk(clk), + .i_switch(btnD), + .o_switch(w_down) +); + +debounce_switch debounce_start( + .clk(clk), + .i_switch(btnL), + .o_switch(w_start) +); + +// flip_flop flip_flop( +// .clk(clk), +// .rst(1'b1), +// .t(w_start), +// .q(w_enable) +// ); + +sr_latch sr_latch( + .C(clk), + .S(~w_up), + .R(~w_down), + .Q(w_direction), + .notQ() +); + +// sr_latch start_latch( +// .C(clk), +// .S(~w_start), +// .R(~w_start&w_enable), +// .Q(w_enable), +// .notQ() +// ); + bin_7segment bin_7segment( .clk(clk1kHz), // clock working with 10kHz .in(w_counter), // input diff --git a/ld2/top_tb.v b/ld2/top_tb.v index c306191..ae273ac 100644 --- a/ld2/top_tb.v +++ b/ld2/top_tb.v @@ -29,43 +29,42 @@ `include "7segment.v" `include "debounce_switch.v" `include "counter.v" +`include "sr_latch.v" +`include "flip_flop.v" //top module `include "top.v" -module top_tb#( parameter - WAIT = 1, - WAIT_WIDTH = 2, - SPEED = 2, - //memory parameters - ADDR_WIDTH = 17, //19, // - DATA_WIDTH = 12, - DEPTH = 307_200//76_800, // -)(); +module top_tb(); reg clk = 1'b0; reg reset = 1'b0; reg [3:0] sw = 4'b0000; +reg start = 1'b0; +reg up = 1'b0; // 50% duty cycle clock always #0.5 clk <= ~clk; - -reg RsRx; -wire RsTx; - top Test_Unit( .clk(clk), .sw(sw), + .btnU(up), + .btnD(), + .btnL(start), .btnC(reset) ); initial begin + start = 1; + up = 1; #1_000_000; $display("*"); #1_000_000; $display("*"); + start = 0; + up = 0; #1_000_000; $display("*"); #1_000_000;