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Added clock divider 22050Hz. Tested!

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This commit is contained in:
Imants Pulkstenis
2020-06-09 00:04:30 +03:00
parent af6516eb85
commit 13a5336975
5 changed files with 131 additions and 34 deletions
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ld3/dds_vhdl/dds_vhdl.qpf → ld3/dds_vhdl/sin_gen.qpf
+1 -1
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@@ -28,4 +28,4 @@ DATE = "22:16:23 March 21, 2018"
# Revisions
PROJECT_REVISION = "dds_vhdl"
PROJECT_REVISION = "sin_gen"
ld3/dds_vhdl/dds_vhdl.qsf → ld3/dds_vhdl/sin_gen.qsf
+4 -4
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@@ -26,7 +26,7 @@
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dds_vhdl_assignment_defaults.qdf
# sin_gen_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -39,12 +39,12 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY dds_vhdl
set_global_assignment -name TOP_LEVEL_ENTITY sin_gen
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:16:23 MARCH 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name VHDL_FILE dds_vhdl_tb.vhd
set_global_assignment -name VHDL_FILE dds_vhdl.vhd
set_global_assignment -name VHDL_FILE sin_gen_tb.vhd
set_global_assignment -name VHDL_FILE sin_gen.vhd
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
ld3/dds_vhdl/dds_vhdl.vhd → ld3/dds_vhdl/sin_gen.vhd
+26 -8
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@@ -2,7 +2,7 @@
-- Author - Imants Pulkstenis
-- Date - 04.06.2020
-- Project name - Lab work No3
-- Module name - dds_vhdl
-- Module name - sin_gen
--
-- Detailed module description:
-- DDS sinusoidal signal generator
@@ -19,11 +19,13 @@ use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity dds_vhdl is
entity sin_gen is
generic
(
phase_width : integer := 9;
data_width : integer := 16
data_width : integer := 16;
sampling_f : integer := 4535; -- 100MHz/22050
clock_cnt_width : integer := 13
);
port
(
@@ -31,12 +33,13 @@ port
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
signal_out : out std_Logic_vector(data_width - 1 downto 0);
fs_out : out std_logic --output sampling clock for debuging
);
end dds_vhdl;
end sin_gen;
--define inside of the module
architecture behavioral of dds_vhdl is
architecture behavioral of sin_gen is
--define inside use signals
type rom_table is array ( 0 to 2**phase_width - 1) of std_logic_vector(data_width - 1 downto 0);
@@ -560,13 +563,17 @@ architecture behavioral of dds_vhdl is
-- phase counter
signal phase_cnt : unsigned(phase_width - 1 downto 0) := (others => '0');
-- clock divider counter - for generating 22050Hz fs clock
signal clock_cnt : unsigned(clock_cnt_width - 1 downto 0) := (others => '0');
-- clock output
signal clock_out : std_logic := '0';
begin --define the operation of the module!
--phase output for debugging
phase_out <= std_logic_Vector(phase_cnt);
--clcock output for debugiung
fs_out <= std_logic(clock_out);
--phase counter
process(clk)
@@ -574,8 +581,19 @@ begin --define the operation of the module!
if rising_edge(clk) then
if rst = '1' then
phase_cnt <= (others => '0');
clock_cnt <= (others => '0');
else
if clock_cnt <= sampling_f then
clock_cnt <= unsigned(clock_cnt) + 1;
--if clock_cnt = (sampling_f-1)/2 then
-- clock_out <= not clock_out;
--end if;
else
phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr);
clock_cnt <= (others => '0');
clock_out <= not clock_out;
end if;
end if;
end if;
end process;
ld3/dds_vhdl/sin_gen_sum.vhd
+80
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@@ -0,0 +1,80 @@
-----------------------------
-- Author - Imants Pulkstenis
-- Date - 08.06.2020
-- Project name - Lab work No3
-- Module name - sin_gen_sum
--
-- Detailed module description:
-- This is top module containing
-- signal genrators, FIR and IIR filter
--
-- Revision:
-- A - initial design
-- B -
--
-----------------------------
library ieee; --always use this library
use ieee.std_logic_1164.all; --always use this library
use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity sin_gen_sum is
generic
(
phase_width : integer := 9;
data_width : integer := 16;
phase_incr_one : integer := 16;
phase_incr_two : integer := 16
);
port
(
clk : in std_logic; --100mhz clock
rst : in std_logic; --rst
--phase_incr_one : in std_Logic_vector(phase_width - 1 downto 0); --"frequency for first signal"
--phase_incr_two : in std_Logic_vector(phase_width - 1 downto 0); --"frequency for second signal"
signal_out : out std_Logic_vector(data_width - 1 downto 0)
);
end sin_gen_sum;
--define inside of the module
architecture behavioral of sin_gen_sum is
--define inside use signals
--define components to use
component sin_gen is
generic
(
phase_width : integer := 9;
data_width : integer := 16
);
port
(
clk : in std_logic; --100mhz clock
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
);
end component;
begin --define the operation of the module!
dds_vhdl_one : sin_gen
generic map
(
phase_width => phase_width,
data_width => data_width
)
port map
(
clk => clk,
rst => rst,
phase_incr => phase_incr,
phase_out => phase_out,
signal_out => signal_out
);
end behavioral;
ld3/dds_vhdl/dds_vhdl_tb.vhd → ld3/dds_vhdl/sin_gen_tb.vhd
+17 -18
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@@ -1,15 +1,11 @@
-----------------------------
-- Author
-- Date
-- Project name
-- Module name
-- Author Imants Pulkstenis
-- Date 08.06.2020
-- Project name Labwork No3
-- Module name sin_gen_tb
--
-- Detailed module description
--
--
--
--
--
-- Test bench for signal generator
--
--
-- Revision:
@@ -24,16 +20,16 @@ use ieee.numeric_std.all; --use this library if arithmetic required
--define connections to outside
entity dds_vhdl_tb is
entity sin_gen_tb is
generic
(
phase_width : integer := 9;
data_width : integer := 16
);
end dds_vhdl_tb;
end sin_gen_tb;
--define inside of the module
architecture behavioral of dds_vhdl_tb is
architecture behavioral of sin_gen_tb is
--signals
signal clk : std_logic := '0'; --100mhz clock
@@ -41,9 +37,9 @@ architecture behavioral of dds_vhdl_tb is
signal phase_incr : std_Logic_vector(phase_width - 1 downto 0) := (others => '0'); --"frequency"
signal phase_out : std_Logic_vector(phase_width - 1 downto 0) := (others => '0');
signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
--signal fs_out : std_logic := '0';
--define components to use
component dds_vhdl is
component sin_gen is
generic
(
phase_width : integer := 9;
@@ -55,7 +51,8 @@ architecture behavioral of dds_vhdl_tb is
rst : in std_logic; --rst
phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
phase_out : out std_Logic_vector(phase_width - 1 downto 0);
signal_out : out std_Logic_vector(data_width - 1 downto 0)
signal_out : out std_Logic_vector(data_width - 1 downto 0)--;
--fs_out : in std_logic
);
end component;
@@ -68,7 +65,7 @@ begin
clk <= not clk after clk_period/2;
uut : dds_vhdl
uut : sin_gen
generic map
(
phase_width => phase_width,
@@ -80,7 +77,8 @@ begin
rst => rst,
phase_incr => phase_incr,
phase_out => phase_out,
signal_out => signal_out
signal_out => signal_out--,
--fs_out => fs_out
);
@@ -93,7 +91,8 @@ begin
wait for clk_period/2;
--phase_incr <= (0 => '1', others => '0'); --1
phase_incr <= (1 => '1', others => '0'); --2
--phase_incr <= (5 => '1',2 => '1', 1=> '1', others => '0'); --37
phase_incr <= (5 => '1',4 => '1',3 => '1', 0=> '1', others => '0'); --57
wait;
end process;