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 * Copyright (c) 2012, Texas Instruments Incorporated
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 *******************************************************************************
 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//******************************************************************************
//  MSP430F20xx Demo - WDT+ periodic reset
//
//  Description; Various reset intervals are configured in watchdog mode.
//  To illustrate the speed of the reset time the LED flashes in accordance 
//  of the selected interval. 
//
//  ACLK = 32khz, MCLK = SMCLK = default DCO
//
//		  MSP430F20xx
//             -----------------
//         /|\|              XIN|-
//          | |                 |
//          --|RST          XOUT|-
//            |                 |
//            |             P1.0|-->LED
//
//  R. B. Elliott  / H. Grewal
//  Texas Instruments Inc.
//  April 2007
//  Built with IAR Embedded Workbench Version: 3.42A
//******************************************************************************

#include <msp430.h>

int main(void)
{
                                            // WDT is clocked by fSMCLK (1MHz)
  WDTCTL = WDT_MRST_32;                       // ~32ms interval (default)
  //WDTCTL = WDT_MRST_8;                      // ~8ms
  //WDTCTL = WDT_MRST_0_5;                    // ~0.5ms
  //WDTCTL = WDT_MRST_0_064;                  // ~0.064ms
                                            // WDT is clocked by fACLK (32KHz) 
  //WDTCTL = WDT_ARST_1000;                   // 1000ms
  //WDTCTL = WDT_ARST_250;                    // 250ms
  //WDTCTL = WDT_ARST_16;                     // 16ms  
  //WDTCTL = WDT_ARST_1_9;                    // 1.9ms
  P1DIR |= 0x01;
  P1OUT ^=0x01;

  __bis_SR_register(LPM0_bits + GIE);       // Enter LPM3 w/interrupt
}