; --COPYRIGHT--,BSD_EX ; Copyright (c) 2012, Texas Instruments Incorporated ; All rights reserved. ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions ; are met: ; ; * Redistributions of source code must retain the above copyright ; notice, this list of conditions and the following disclaimer. ; ; * Redistributions in binary form must reproduce the above copyright ; notice, this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; ; * Neither the name of Texas Instruments Incorporated nor the names of ; its contributors may be used to endorse or promote products derived ; from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; ; ****************************************************************************** ; ; MSP430 CODE EXAMPLE DISCLAIMER ; ; MSP430 code examples are self-contained low-level programs that typically ; demonstrate a single peripheral function or device feature in a highly ; concise manner. For this the code may rely on the device's power-on default ; register values and settings such as the clock configuration and care must ; be taken when combining code from several examples to avoid potential side ; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware ; for an API functional library-approach to peripheral configuration. ; ; --/COPYRIGHT-- ;******************************************************************************* ; MSP430F20xx Demo - LFXT1 Oscillator Fault Detection ; ; Description: System runs normally in LPM3 with WDT timer clocked by ; 32kHz ACLK with a 1x4 second interrupt. P1.0 is normally pulsed every ; second inside WDT interrupt. If an LFXT1 oscillator fault occurs, ; NMI is requested forcing exit from LPM3. P1.0 is toggled rapidly by software ; as long as LFXT1 oscillator fault is present. Assumed only LFXT1 as NMI ; source - code does not check for other NMI sources. ; ACLK = LFXT1 = 32768, MCLK = SMCLK = Default DCO ; ; //*External watch crystal on XIN XOUT is required for ACLK*// ; ; ; MSP430F20xx ; --------------- ; /|\| XIN|- ; | | | 32kHz ; --|RST XOUT|- ; | | ; | P1.0|-->LED; ; ; P.Thanigai ; Texas Instruments Inc. ; May 2007 ; Built with Code Composer Essentials Version: 2.0 ;******************************************************************************* .cdecls C,LIST, "msp430.h" ;------------------------------------------------------------------------------- .def RESET ; Export program entry-point to ; make it known to linker. ;------------------------------------------------------------------------------ .text ; Program Start ;------------------------------------------------------------------------------ RESET mov.w #0280h,SP ; Initialize stackpointer StopWDT mov.w #WDT_ADLY_1000,&WDTCTL ; WDT 1s interval timer bis.b #WDTIE,&IE1 ; Enable WDT interrupt SetupP1 mov.b #0FFh,&P1DIR ; All P1.x outputs clr.b &P1OUT ; All P1.x reset SetupP2 mov.b #0FFh,&P2DIR ; All P2.x outputs clr.b &P2OUT ; All P2.x reset ; An immedate Osc Fault will occur next bis.b #OFIE,&IE1 ; Enable osc fault interrupt ; Mainloop xor.b #001h,&P1OUT ; Toggle P1.0 bis.w #LPM3+GIE,SR ; Enter LPM3, enable interrupts jmp Mainloop ; ; ;------------------------------------------------------------------------------- NMI_ISR; Only osc fault enabled, R15 used temporarily and not saved ; Assumed LFXT1 is only source for NMI interrupt ;------------------------------------------------------------------------------- CheckOsc bic.b #OFIFG,&IFG1 ; Clear OSC fault flag xor.b #001h,&P1OUT ; Toggle P1.0 mov.w #03FFFh,R15 ; R15 = Delay CheckOsc1 dec.w R15 ; Time for flag to set jnz CheckOsc1 ; bit.b #OFIFG,&IFG1 ; OSC fault flag set? jnz CheckOsc ; OSC Fault, clear flag again bis.b #OFIE,&IE1 ; re-enable osc fault interrupt reti ; return from interrupt ; ;------------------------------------------------------------------------------- WDT_ISR; Exit LPM3 on reti ;------------------------------------------------------------------------------- bic.w #LPM3,0(SP) ; reti ; ; ;------------------------------------------------------------------------------ ; Interrupt Vectors ;------------------------------------------------------------------------------ .sect ".reset" ; MSP430 RESET Vector .short RESET ; .sect ".int10" ; WDT Vector .short WDT_ISR ; .sect ".int14" ; NMI Vector .short NMI_ISR .end