83 lines
2.4 KiB
Verilog
83 lines
2.4 KiB
Verilog
// Default parameters for image transform module
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// Four MSB are actual registers
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// next two bits are one of modes selected by swishes. 4 modes are avilable
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// LSB are camera bit. avilable two cameras. Camera 0 and camera 1.
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//
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//
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module default_reg_writer #(parameter
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CAM_LINE = 9,
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CAM_PIXEL = 10,
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TRA_IMG_WIDTH = 'd320,
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TRA_IMG_DEPTH = 'd240,
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T11 = 25'sb0_000000000000_100000000000,
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T12 = 25'sb0_000000000000_000000000000,
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T13 = 25'sb0_000000000000_000000000000,
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T21 = 25'sb0_000000000000_000000000000,
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T22 = 25'sb0_000000000000_100000000000,
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T23 = 25'sb0_000000000000_000000000000,
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T31 = 25'sb0_000000000000_000000000000,
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T32 = 25'sb0_000000000000_000000000000,
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T33 = 25'sb0_000000000001_000000000000
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)(
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input clk,
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input i_enable,
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input i_reset,
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output o_configured,
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output [6:0] o_addr ,
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output [24:0] o_data ,
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output o_we
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);
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// Internal variables and registers
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reg r_configured = 0;
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reg [6:0] r_divider = 7'b0000001; // this value gives a 127 cycle pause before the initial frame is sent
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reg [6:0] r_count = 'b0;
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reg [24:0] r_data = 'b0;
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reg r_we = 'b0;
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//------------------ synchonus logic------------------
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always @ (posedge clk) begin
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if(i_enable)begin
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if (i_reset || r_divider != 0 ) begin
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r_count <= 0;
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r_divider <= r_divider + 1;
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r_configured <= 0;
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if (r_divider == 'd127) r_we <= 1;
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else r_we <= 0;
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end
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else if ( r_count < 88 ) begin
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r_count <= r_count + 1;
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r_we <= 1;
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end
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end
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case (r_count[6:3])
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'd0 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH;
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'd1 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH;
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'd2 : r_data <= T11;
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'd3 : r_data <= T12;
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'd4 : r_data <= T13;
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'd5 : r_data <= T21;
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'd6 : r_data <= T22;
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'd7 : r_data <= T23;
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'd8 : r_data <= T31;
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'd9 : r_data <= T32;
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'd10 : r_data <= T33;
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default: begin
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r_configured <= 1; // default case just in case do nothing
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r_we <= 0;
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end
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endcase
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end
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//----------- combinational logic ----------------------
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assign o_configured = r_configured;
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assign o_addr = r_count;
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assign o_data = r_data;
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assign o_we = r_we;
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endmodule |