424 lines
11 KiB
Verilog
424 lines
11 KiB
Verilog
// TOP module
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//
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//
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// `include "clock_divider_param.v"
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// `include "clock_enable_param.v"
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// `include "blockram2.v"
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// `include "pattern_gen.v"
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// `include "vga_module.v"
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// `include "horizontal_counter.v"
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// `include "vertical_counter.v"
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// `include "UART_Loopback_module.v"
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// `include "UART_TX.v"
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// `include "UART_RX.v"
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// `include "7segment_v2.v"
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// `include "com_to_mem_FSM_hex.v"
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// `include "com_to_mem_module.v"
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// `include "ov7670_top.v"
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// `include "debounce_switch.v"
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// `include "ov7670_capture.v"
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// `include "ov7670_controller.v"
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// `include "imag_procesor.v"
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// `include "default_reg_writer.v"
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// `include "i2c_senderv2.v"
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// `include "ov7670_registers.v"
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// `include "imag_save.v"
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// `include "rgb2gray.v"
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// `include "rgb2gray2.v"
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// `include "imag_transform.v"
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// `include "reg_reader.v"
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// `include "address_gen.v"
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// `include "overlay.v"
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// `include "two_cam_one_screen2.v"
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// `include "lookuptable.v"
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module top #( parameter
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//pattern generator paremater
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SPEED = 300,
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//enable signal parameters
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WAIT = 1,
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WAIT_WIDTH = 2,
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//memory parameters
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ADDR_WIDTH = 17, // 19, //
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DATA_WIDTH = 12,
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DEPTH = 76_800, // 307_200,//
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//VGA parameters
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HSYNC_CLKS = 800,
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HSYNC_DISPLAY = 640,
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HSYNC_PULSE = 96,
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HSYNC_FRONT_PORCH = 16,
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HSYNC_BACK_PORCH = 48,
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VSYNC_LINES = 521,
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VSYNC_DISPLAY = 480,
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VSYNC_PULSE = 2,
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VSYNC_FRONT_PORCH = 10,
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VSYNC_BACK_PORCH = 29,
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// CAM buss
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CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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)(
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input clk,
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output [11:0] led,
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output [1:0] ledc, // led camera configuration indicator
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//VGA inputs outputs
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output [3:0] vgaRed,
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output [3:0] vgaBlue,
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output [3:0] vgaGreen,
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output Hsync,
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output Vsync,
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input [3:0] sw,
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input [8:0] im_p,
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//UART
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input RsRx, // UART RX Data
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output RsTx, // UART TX Data
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// 7 segment
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output [6:0] seg,
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output [3:0] an,
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// camera inputs outputs
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input ov7670_cam1_pclk,
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output ov7670_cam1_mclk,
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input ov7670_cam1_vs,
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input ov7670_cam1_hs,
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input [7:0] ov7670_cam1_data,
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output ov7670_cam1_scl,
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inout ov7670_cam1_sda,
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output ov7670_cam1_pwdn,
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output ov7670_cam1_reset,
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input ov7670_cam2_pclk,
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output ov7670_cam2_mclk,
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input ov7670_cam2_vs,
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input ov7670_cam2_hs,
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input [7:0] ov7670_cam2_data,
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output ov7670_cam2_scl,
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inout ov7670_cam2_sda,
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output ov7670_cam2_pwdn,
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output ov7670_cam2_reset,
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input btnC, // reconfigure camera
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input btnU // reset button for registers blobk RAM
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);
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//------internal wires and registers--------
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wire w_enable;
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wire pixel_clk;
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wire clk50;
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wire w_write;
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wire [ADDR_WIDTH-1:0] w_addr_wr;
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wire [DATA_WIDTH-1:0] w_data_wr;
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wire [ADDR_WIDTH-1:0] w_com_addr_wr;
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wire [DATA_WIDTH-1:0] w_com_data_wr;
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wire w_com_write;
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wire [ADDR_WIDTH-1:0] w_com_addr_rd;
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// wire [ADDR_WIDTH-1:0] w_addrb;
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wire [ADDR_WIDTH-1:0] w_addr_rd;
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wire [DATA_WIDTH-1:0] w_data_rd;
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wire [DATA_WIDTH-1:0] w_camera_cam1_data_wr;
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wire w_camera_cam1_we;
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wire [CAM_LINE-1:0] w_line_cam1;
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wire [CAM_PIXEL-1:0] w_pixel_cam1;
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wire [DATA_WIDTH-1:0] w_camera_cam2_data_wr;
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wire w_camera_cam2_we;
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wire [CAM_LINE-1:0] w_line_cam2;
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wire [CAM_PIXEL-1:0] w_pixel_cam2;
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wire [ADDR_WIDTH-1:0] w_proces_addr_wr;
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wire [DATA_WIDTH-1:0] w_proces_data_wr;
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wire w_proces_we;
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wire [DATA_WIDTH-1:0] w_doa_bram;
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wire w_wea_bram;
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wire [ADDR_WIDTH-1:0] w_addra_bram;
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wire [DATA_WIDTH-1:0] w_dia_bram;
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reg [DATA_WIDTH-1:0] r_led = 0;
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wire w_config_default ;
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wire [6:0] w_addr_default ;
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wire [24:0] w_data_default ;
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wire w_we_default ;
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wire w_reset_default;
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wire [DATA_WIDTH-1:0] w_doa_bram_old;
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wire [24:0] w_data_reg;
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wire [6:0] w_addr_rd_reg;
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wire [6:0] w_addr_com_wr_reg ;
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wire [24:0] w_data_com_reg ;
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wire w_we_com_reg ;
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wire [8:0] w_im_p;
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//-----sub modules--------------------------
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clock_enable_param #(
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.WAIT(WAIT),
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.WIDTH(WAIT_WIDTH)
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) clock_enable1 (
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.clk(clk),
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.enable(w_enable)
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);
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clock_divider #(
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.DIVIDER(2),
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.WIDTH(3)
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) clk25mhz_gen (
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.clk(clk),
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.clk_out(pixel_clk)
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);
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clock_divider #(
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.DIVIDER(1),
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.WIDTH(3)
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) clk50mhz_gen (
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.clk(clk),
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.clk_out(clk50)
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);
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pattern_gen #(
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.DEPTH(DEPTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.SPEED(SPEED)
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) pattern_gen1 (
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.clk(clk),
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// .sw(sw[1]),
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.i_enable(w_enable),
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.o_addr(w_addr_wr),
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.o_data(w_data_wr),
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.o_write(w_write)
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);
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rams_tdp_rf_rf #(
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.DEPTH(DEPTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH))
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bram3(
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// -------------------------PORT A
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.clka(clk),
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.ena( 1'b1 /*w_enable*/),
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.wea( w_wea_bram ),
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.addra( w_addra_bram ),
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.dia( w_dia_bram ),
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.doa( w_doa_bram ),
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//---------------------------PORT B
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.clkb(clk),
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.addrb( w_addr_rd ),
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.enb(w_enable),
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//.web(),
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//.dib(),
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.dob(w_data_rd));
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vga_module #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH),
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.HSYNC_CLKS(HSYNC_CLKS),
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.HSYNC_DISPLAY(HSYNC_DISPLAY),
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.HSYNC_PULSE(HSYNC_PULSE),
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.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
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.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
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.VSYNC_LINES(VSYNC_LINES) ,
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.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
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.VSYNC_PULSE(VSYNC_PULSE) ,
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.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
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.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
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) vga_module1 (
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.clk(pixel_clk),
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.o_vgaRed(vgaRed),
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.o_vgaBlue(vgaBlue),
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.o_vgaGreen(vgaGreen),
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.o_Hsync(Hsync),
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.o_Vsync(Vsync),
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.o_display(),
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.o_addr_rd(w_addr_rd),
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.o_data_rd(w_data_rd)
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);
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com_to_mem #(
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.WAIT(WAIT),
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.WAIT_WIDTH(WAIT_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH)
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) com_to_mem1 (
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.clk(clk),
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.sw(sw[0]),
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//.i_data_rd(w_doa_bram),
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.i_enable(w_enable),
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.o_addr_wr(w_com_addr_wr),
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.o_addr_rd(w_com_addr_rd),
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.o_data_wr(w_com_data_wr),
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.o_write(w_com_write),
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.RsRx(RsRx), // UART RX Data
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.RsTx(RsTx), // UART TX Data
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.seg(seg),
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.an(an),
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.o_addr_wr_reg(w_addr_com_wr_reg),
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.o_data_reg(w_data_com_reg),
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.o_we_reg(w_we_com_reg)
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);
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ov7670_top #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) ov7670_cam1(
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.clk(pixel_clk),
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.btn(btnC),
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.config_finished(ledc[0]), // configuration finished
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.o_data_wr(w_camera_cam1_data_wr),
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.o_line(w_line_cam1),
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.o_pixel(w_pixel_cam1),
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.we(w_camera_cam1_we),
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.ov7670_pclk(ov7670_cam1_pclk),
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.ov7670_mclk(ov7670_cam1_mclk),
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.ov7670_vs(ov7670_cam1_vs),
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.ov7670_hs(ov7670_cam1_hs),
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.ov7670_data(ov7670_cam1_data),
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.ov7670_scl(ov7670_cam1_scl),
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.ov7670_sda(ov7670_cam1_sda),
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.ov7670_pwdn(ov7670_cam1_pwdn),
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.ov7670_reset(ov7670_cam1_reset)
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);
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ov7670_top #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) ov7670_cam2(
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.clk(pixel_clk),
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.btn(btnC),
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.config_finished(ledc[1]),
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.o_data_wr(w_camera_cam2_data_wr),
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.o_line(w_line_cam2),
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.o_pixel(w_pixel_cam2),
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.we(w_camera_cam2_we),
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.ov7670_pclk(ov7670_cam2_pclk),
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.ov7670_mclk(ov7670_cam2_mclk),
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.ov7670_vs(ov7670_cam2_vs),
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.ov7670_hs(ov7670_cam2_hs),
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.ov7670_data(ov7670_cam2_data),
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.ov7670_scl(ov7670_cam2_scl),
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.ov7670_sda(ov7670_cam2_sda),
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.ov7670_pwdn(ov7670_cam2_pwdn),
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.ov7670_reset(ov7670_cam2_reset)
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);
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imag_procesor #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) imag_procesor(
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.im_p(w_im_p),
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.clk(clk),
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.clk25(pixel_clk),
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.clk50(clk50),
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.i_enable(w_enable),
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.i_data_reg(w_data_reg),
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.o_addr_rd_reg(w_addr_rd_reg),
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.i_we_cam2(w_camera_cam2_we),
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.i_data_cam2_wr(w_camera_cam2_data_wr),
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.i_line_cam2(w_line_cam2),
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.i_pixel_cam2(w_pixel_cam2),
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.i_we_cam1(w_camera_cam1_we),
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.i_data_cam1_wr(w_camera_cam1_data_wr),
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.i_line_cam1(w_line_cam1),
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.i_pixel_cam1(w_pixel_cam1),
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.o_we(w_proces_we),
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.o_addr_wr(w_proces_addr_wr),
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.o_data_wr(w_proces_data_wr)
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);
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rams_tdp_rf_rf #(
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.DEPTH(88),
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.ADDR_WIDTH(7),
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.DATA_WIDTH(25))
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bram_reg(
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// -------------------------PORT A
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.clka( clk),
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.ena( 1'b1 /*w_enable*/ ),
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.wea( ),
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.addra(w_addr_rd_reg),
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.dia( ),
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.doa(w_data_reg),
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//---------------------------PORT B
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.clkb( clk),
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.addrb( w_config_default ? w_addr_com_wr_reg : w_addr_default ),
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.enb( w_enable),
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.web( w_config_default ? w_we_com_reg : w_we_default),
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.dib( w_config_default ? w_data_com_reg : w_data_default),
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.dob() // not connected
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);
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default_reg_writer default_reg_writer1(
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.clk(clk),
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.i_enable(w_enable),
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.i_reset(w_reset_default),
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.o_configured(w_config_default),
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.o_addr(w_addr_default),
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.o_data(w_data_default) ,
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.o_we(w_we_default)
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);
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debounce_switch debounce_switch_reset(
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.clk(clk),
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.i_switch(btnU),
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.o_switch(w_reset_default)
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);
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mode_selector mode_selector(
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.clk(clk),
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// .i_enable(w_enable),
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.i_im_p(im_p),
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.autoselect(sw[3]),
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.o_im_p(w_im_p)
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);
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always@(posedge clk) begin
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if (~w_wea_bram) begin
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r_led <= w_doa_bram;
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// r_doa_bram_old <= w_doa_bram;
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end
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else begin
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r_led <= w_doa_bram_old;
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end
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end
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assign led[11:0] = r_led ;
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assign w_doa_bram_old = r_led;
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assign w_addra_bram = ~w_wea_bram ? w_com_addr_rd : // if we LOW port A address connected to com_to_mem module
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(sw[2:1] == 2'b00) ? w_com_addr_wr :
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(sw[2:1] == 2'b01) ? w_addr_wr :
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(sw[2:1] == 2'b10) ? w_proces_addr_wr :
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w_proces_addr_wr ; // sw[2:1] == 2'b11
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assign w_wea_bram = (sw[2:1] == 2'b00) ? w_com_write :
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(sw[2:1] == 2'b01) ? w_write :
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(sw[2:1] == 2'b10) ? w_proces_we :
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w_proces_we ; // sw[2:1] == 2'b11
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assign w_dia_bram = (sw[2:1] == 2'b00) ? w_com_data_wr :
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(sw[2:1] == 2'b01) ? w_data_wr :
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(sw[2:1] == 2'b10) ? w_proces_data_wr :
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w_proces_data_wr ;
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endmodule |