72 lines
2.1 KiB
Verilog
72 lines
2.1 KiB
Verilog
module rgb2gray #(
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parameter r_koef = 17, // 0.3 in binary
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g_koef = 37, // 0.59 in binary
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b_koef = 7 , // 0.11 in binary
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CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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) (
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input clk,
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input gray, // outputs gray if HIGH
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// input form camera
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input i_we,
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input [CAM_DATA_WIDTH-1:0] i_data_wr,
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input [CAM_LINE-1:0] i_line,
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input [CAM_PIXEL-1:0] i_pixel,
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// output
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output o_we,
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output [CAM_DATA_WIDTH-1:0] o_data_wr,
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output [CAM_LINE-1:0] o_line,
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output [CAM_PIXEL-1:0] o_pixel
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);
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//------------Internal variables and constants-----------
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reg r_we1 = 0;
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reg r_we2 = 0;
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reg r_we3 = 0;
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reg [CAM_LINE-1:0] r_line1;
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reg [CAM_LINE-1:0] r_line2;
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reg [CAM_LINE-1:0] r_line3;
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reg [CAM_PIXEL-1:0] r_pixel1;
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reg [CAM_PIXEL-1:0] r_pixel2;
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reg [CAM_PIXEL-1:0] r_pixel3;
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reg [10:0] r_red1 = 0;
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reg [10:0] r_green1 = 0;
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reg [10:0] r_blue1 = 0;
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reg [10:0] r_data2 = 0;
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reg [10:0] r_data3 = 0;
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always@(posedge clk) begin
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// 3rd cycle
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r_we3 <= r_we2;
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r_pixel3 <= r_pixel2;
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r_line3 <= r_line2;
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r_data3 <= r_data2;
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// second cycle
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r_we2 <= r_we1;
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r_pixel2 <= r_pixel1;
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r_line2 <= r_line1;
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r_data2 <= r_red1 + r_green1 + r_blue1;
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// first cycle
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r_we1 <= i_we;
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r_pixel1 <= i_pixel;
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r_line1 <= i_line;
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r_red1 <= i_data_wr[11:8] * r_koef;
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r_green1 <= i_data_wr[7:4] * g_koef;
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r_blue1 <= i_data_wr[3:0] * r_koef;
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end
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assign o_we = ~gray ? i_we : r_we3;
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assign o_line = ~gray ? i_line : r_line3;
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assign o_pixel = ~gray ? i_pixel : r_pixel3;
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assign o_data_wr = ~gray ? i_data_wr :
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r_data3[10] ?
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12'hfff : {r_data3[9:6],r_data3[9:6],r_data3[9:6]}; // if overflow send all 1
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endmodule |