71 lines
1.2 KiB
Verilog
71 lines
1.2 KiB
Verilog
// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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`include "pattern_gen.v"
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`include "clock_enable_param.v"
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module pattern_gen_tb#( parameter
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ADDR_WIDTH = 17,
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DATA_WIDTH = 8
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) ();
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// for clock_divider
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reg clk = 1'b0;
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wire enable;
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wire [ADDR_WIDTH-1:0] addr ;
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wire [DATA_WIDTH-1:0] data ;
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// generate clk
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always #0.5 clk <= ~clk;
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initial
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begin
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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#76_800;
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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clock_enable_param #(
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.WAIT(1),
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.WIDTH(2)
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) clock_enable1 (
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.clk(clk),
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.enable(enable));
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address_gen #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) test_unit (
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.clk(clk),
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.i_enable(enable),
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.o_addr(addr),
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.o_data(data));
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endmodule |