150 lines
3.4 KiB
Verilog
150 lines
3.4 KiB
Verilog
// This module generates color patherns and rwite them in
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// BlockRAM memory
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//
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module pattern_gen #( parameter
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LINES = 480,
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COLUMNS = 640,
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DEPTH = 76_800, //307_200, //
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ADDR_WIDTH = 17,
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DATA_WIDTH = 12,
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SPEED = 2,
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SIZE = 2
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)(
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input clk,
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input i_enable,
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// input sw,
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output [ADDR_WIDTH-1:0] o_addr,
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output [DATA_WIDTH-1:0] o_data,
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output o_write);
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//-------------Internal Constants---------------------------
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//reg [ADDR_WIDTH-1:0] counter_reg = 'b0;
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reg [31:0] speed_counter_reg = 'b0;
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//reg [DATA_WIDTH-1:0] color_reg = 'b0;
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reg [3:0] red_reg = 'b0;
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reg [3:0] blue_reg = 'b0;
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reg [3:0] green_reg = 'b0;
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reg [8:0] line_reg = 'b0;
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reg [9:0] column_reg = 'b0;
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reg write_reg=1'b0;
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/*
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localparam [SIZE-1:0] GREEN = 'h0,
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RED = 'h1,
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BLUE = 'h2;
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reg [SIZE-1:0] state_reg=GREEN, next_reg=GREEN;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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if (i_enable) begin
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state_reg <= next_reg;
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end
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end
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*/
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//----next state & outputs, combinational always block------
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always @(posedge clk) begin
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speed_counter_reg <= speed_counter_reg + 1;
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if(speed_counter_reg == SPEED) begin
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write_reg <= 1'b1;
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speed_counter_reg <= 0;
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if(i_enable) begin
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// counter_reg <= counter_reg + 1;
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if(column_reg < COLUMNS-1) begin
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column_reg <= column_reg + 1 ;
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end
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else begin
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column_reg <= 0;
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if (line_reg< LINES -1 ) begin
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line_reg <= line_reg + 1;
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end
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else begin
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line_reg <= 0;
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end
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end
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/*
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if (line_reg < 239 ) begin
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green_reg <= 4'b1111;
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end
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else begin
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green_reg <= 4'b0000;
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end
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*/
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/*
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if (column_reg < 319 || column_reg == 639) begin
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red_reg <= 4'b1111;
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end
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else begin
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red_reg <= 4'b0000;
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end
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*/
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/*
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case (state_reg)
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GREEN : begin
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color_reg <= 12'b111100000000;
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if(counter_reg == DEPTH - 1) begin
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next_reg <= RED;
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counter_reg <= 'b0;
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end
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end
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RED : begin
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color_reg <= 12'b000011110000;
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if(counter_reg == DEPTH - 1 ) begin
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next_reg <= BLUE;
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counter_reg <= 'b0;
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end
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end
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BLUE : begin
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color_reg <= 12'b000000001111;
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if(counter_reg == DEPTH - 1) begin
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next_reg <= GREEN;
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counter_reg <= 'b0;
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end
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end
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default: begin
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next_reg <= GREEN ;
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counter_reg <= 'b0;
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end
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endcase
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*/
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end
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end
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else if (i_enable) write_reg <= 1'b0;
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end
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always@* begin
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if (line_reg < 239 ) begin
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green_reg <= 4'b1111;
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end
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else begin
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green_reg <= 4'b0000;
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end
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if (column_reg > 319 ) begin
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red_reg <= 4'b1111;
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end
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else begin
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red_reg <= 4'b0000;
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end
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end
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assign o_addr = (line_reg[8:1] * COLUMNS/2) + column_reg [9:1] ;
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assign o_data = {green_reg, red_reg , blue_reg};
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//assign o_write = sw ? write_reg : 1'b0 ; // remowing switch
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assign o_write = write_reg;
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endmodule |