110 lines
3.3 KiB
Verilog
110 lines
3.3 KiB
Verilog
module overlay #(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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) (
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input clk,
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input enable,
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// input form camera
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input i_we,
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input [CAM_DATA_WIDTH-1:0] i_data,
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input [CAM_LINE-1:0] i_line,
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input [CAM_PIXEL-1:0] i_pixel,
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// image size and does it need to be resized
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input [CAM_LINE-1:0] i_imag_depth,
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input [CAM_PIXEL-1:0] i_imag_width,
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input i_imag_resized,
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output [CAM_LINE-1:0] o_imag_depth,
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output [CAM_PIXEL-1:0] o_imag_width,
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output o_imag_resized,
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// output
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output o_we,
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output [CAM_DATA_WIDTH-1:0] o_data,
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output [CAM_LINE-1:0] o_line,
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output [CAM_PIXEL-1:0] o_pixel
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);
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//------------Internal variables and constants-----------
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reg [CAM_LINE-1:0] r_line = 0;
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reg [CAM_PIXEL-1:0] r_pixel = 0;
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reg [CAM_DATA_WIDTH-1:0] r_data = 0;
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reg r_we = 0;
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//------------ syncronus logic----------------------------
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always@(posedge clk) begin
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if(i_imag_resized) begin
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if (enable) begin
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if (i_line == 40 ||
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i_line == 80 ||
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i_line == 120 ||
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i_line == 160 ||
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i_line == 200 ||
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i_pixel == 40 ||
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i_pixel == 80 ||
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i_pixel == 120 ||
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i_pixel == 160 ||
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i_pixel == 200 ||
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i_pixel == 240 ||
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i_pixel == 280 ) begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= 12'h0f0;
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r_we <= i_we;
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end else begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= i_data;
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r_we <= i_we;
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end
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end else begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= i_data;
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r_we <= i_we;
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end
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end
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else begin
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if (enable) begin
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if (i_line == 80 ||
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i_line == 160 ||
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i_line == 240 ||
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i_line == 320 ||
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i_line == 400 ||
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i_pixel == 80 ||
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i_pixel == 160 ||
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i_pixel == 240 ||
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i_pixel == 320 ||
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i_pixel == 400 ||
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i_pixel == 480 ||
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i_pixel == 560
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) begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= 12'h0f0;
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r_we <= i_we;
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end else begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= i_data;
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r_we <= i_we;
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end
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end else begin
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r_line <= i_line;
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r_pixel <= i_pixel;
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r_data <= i_data;
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r_we <= i_we;
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end
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end
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end
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//------------ output logic -----------------------------
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assign o_we = r_we;
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assign o_line = r_line;
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assign o_pixel = r_pixel;
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assign o_data = r_data;
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assign o_imag_depth = i_imag_depth;
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assign o_imag_width = i_imag_width;
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assign o_imag_resized = i_imag_resized;
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endmodule |