122 lines
2.3 KiB
Verilog
122 lines
2.3 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 25MHz clock input from top module
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// 50% duty cycle 20ns HIGH and 20ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 10ns
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//sub modules
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`include "i2c_senderv2.v"
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`include "debounce_switch.v"
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`include "ov7670_capture.v"
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`include "ov7670_registers.v"
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`include "ov7670_controller.v"
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//top module
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`include "ov7670_top.v"
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module ov7670_top_tb();
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//--------Internal register-----------
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reg clk = 1'b0;
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reg reset = 1'b0;
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reg send_enable = 1'b0;
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// bidirectional test bench
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// source:
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// https://stackoverflow.com/questions/31391112/bidirectional-port-in-verilog-testbench
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wire input_value;
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wire bidir_signal;
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reg output_value;
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reg output_value_valid;
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reg btn_reg=0;
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assign input_value = bidir_signal;
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assign bidir_signal = (output_value_valid==1'b1)? output_value : 1'hZ;
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//---------Test script----------------
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// 50% duty cycle clock
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always #2 clk <= ~clk;
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//-----Unit Under test---------------
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ov7670_top #(
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)Test_Unit(
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.clk(clk),
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.btn(btn_reg),
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.ov7670_pclk(),
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.ov7670_mclk(),
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.ov7670_vs(),
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.ov7670_hs(),
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.ov7670_data(),
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.ov7670_scl(),
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.ov7670_sda(bidir_signal),
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.ov7670_pwdn(),
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.ov7670_reset()
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);
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// first ACK signal
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initial
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begin
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#0 output_value = 0;
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output_value_valid = 0;
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#8902 output_value = 0;
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output_value_valid = 0;
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#600 output_value = 0;
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output_value_valid = 0;
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end
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// second ACK signal
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initial
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begin
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#16_102 output_value = 0;
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output_value_valid = 0;
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#600 output_value = 0;
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output_value_valid = 0;
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end
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// therd ACK signal
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initial
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begin
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#23_302 output_value = 0;
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output_value_valid = 0;
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#600 output_value = 0;
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output_value_valid = 0;
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end
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initial
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begin
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#0 btn_reg = 0;
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#10_000 btn_reg = 1;
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#10000 btn_reg = 0;
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#50000;
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$display("*");
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#0 btn_reg = 0;
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#10_000 btn_reg = 1;
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#20000000 btn_reg = 0;
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#5000000;
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$display("*");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |