65 lines
1.7 KiB
Verilog
65 lines
1.7 KiB
Verilog
module ov7670_top #(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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)(
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input clk, // 25MHz clk
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output [CAM_DATA_WIDTH-1:0] o_data_wr,
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output we,
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output [CAM_LINE-1:0] o_line,
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output [CAM_PIXEL-1:0] o_pixel,
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output config_finished,
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input btn,
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input ov7670_pclk,
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output ov7670_mclk,
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input ov7670_vs,
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input ov7670_hs,
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input [7:0] ov7670_data,
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output ov7670_scl,
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inout ov7670_sda,
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output ov7670_pwdn,
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output ov7670_reset
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);
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//-----------internal regiters and wires-----------------
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wire resend;
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wire w_finished;
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//---------------sub modules--------------------------
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debounce_switch debounce_switch(
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.clk(clk),
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.i_switch(btn),
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.o_switch(btn_db));
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ov7670_capture #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) ov7670_capture (
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.we(we),
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.reset(btn_db),
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.o_data_wr(o_data_wr),
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.o_line(o_line),
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.o_pixel(o_pixel),
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.ov7670_pclk(ov7670_pclk),
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.ov7670_vs(ov7670_vs),
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.ov7670_hs(ov7670_hs),
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.ov7670_data(ov7670_data)
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);
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ov7670_controller ov7670_controller (
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.clk(clk),
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.ov7670_sda(ov7670_sda),
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.ov7670_scl(ov7670_scl),
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.resend(btn_db),
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.config_finished(config_finished),
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.ov7670_pwdn(ov7670_pwdn),
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.ov7670_reset(ov7670_reset),
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.ov7670_mclk(ov7670_mclk) );
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endmodule |