45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
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module ov7670_controller (
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input clk, // 25MHz input clk
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inout ov7670_sda,
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output ov7670_scl,
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input resend,
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output config_finished,
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output ov7670_pwdn,
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output ov7670_reset,
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output ov7670_mclk );
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//--------------wires and registers----------------------
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wire [15:0] command;
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wire finished;
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wire taken;
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localparam CAMERA_ADDR = 8'h42; // or 8'h21
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//------------controls of camera-------------------------
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assign ov7670_reset = 1'b1; // Normal mode
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assign ov7670_pwdn = 1'b0; // Power device up
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assign ov7670_mclk = clk;
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assign config_finished = finished;
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//-----------sub modules---------------------------------
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i2c_sender i2c_sender (
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.clk(clk),
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.ov7670_sda(ov7670_sda),
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.ov7670_scl(ov7670_scl),
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.taken(taken),
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.send(~finished),
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.id(CAMERA_ADDR),
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.register(command[15:8]),
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.value(command[7:0]) );
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ov7670_registers ov7670_registers (
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.clk(clk),
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.resend(resend),
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.advance(taken),
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.command(command),
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.finished(finished) );
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endmodule |