109 lines
3.0 KiB
Verilog
109 lines
3.0 KiB
Verilog
module ov7670_capture #(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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)(
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output we,
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output [CAM_DATA_WIDTH-1:0] o_data_wr,
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output [CAM_LINE-1:0] o_line,
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output [CAM_PIXEL-1:0] o_pixel,
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input reset,
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input ov7670_pclk,
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input ov7670_vs,
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input ov7670_hs,
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input [7:0] ov7670_data
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);
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//-----------internal regiters and wires-----------------
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reg [1:0] pixel_counter = 'h0;
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/* // YUV grayscale mode
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reg [7:0] u; // U=B-Y
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reg [7:0] v; // V=R-Y
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reg [7:0] y0; // Y=0.59G + 0.31R + 0.11B
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reg [7:0] y1; // Y=0.59G + 0.31R + 0.11B
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*/
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// Color mode RGB 565
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reg [7:0] byte1 = 'h0;
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reg [7:0] byte2 = 'h0;
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reg [7:0] byte3 = 'h0;
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reg [7:0] byte4 = 'h0;
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reg [CAM_LINE-1:0] line = 'h0;
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reg [CAM_PIXEL-1:0] pixel = 'h0;
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reg vsync_old_reg = 'h0;
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reg hsync_old_reg = 'h0;
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//-------------------------------------------------------
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always@(posedge ov7670_pclk)begin
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vsync_old_reg <= ov7670_vs;
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hsync_old_reg <= ov7670_hs;
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end
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//-------------------------------------------------------
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always@(posedge ov7670_pclk || reset)begin
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if (ov7670_hs== 0 || reset == 1) begin
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pixel_counter <= 0;
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end
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if (ov7670_hs == 1 && ov7670_vs== 0 ) begin
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case (pixel_counter)
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/* // YUV grayscale mode
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2'b00: u <= ov7670_data;
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2'b01: y0 <= ov7670_data;
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2'b10: v <= ov7670_data;
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2'b11: y1 <= ov7670_data;
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*/ // RGB color mode
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2'b00: byte1 <= ov7670_data;
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2'b01: byte2 <= ov7670_data;
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2'b10: byte3 <= ov7670_data;
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2'b11: byte4 <= ov7670_data;
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endcase
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if ( pixel_counter[0] == 1 ) begin
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if (pixel < 639 )
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pixel <= pixel +1;
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end
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pixel_counter <= pixel_counter + 1;
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end
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if(hsync_old_reg==1 && ov7670_hs==0) begin
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pixel <= 0;
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line <= line + 1;
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end
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if(vsync_old_reg==1 && ov7670_vs == 0) begin
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line <= 0;
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end
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end
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assign o_pixel = pixel;//[9:1];
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assign o_line = line;//[8:1];
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assign we = (pixel_counter[0]==1'b1) ? 1'b1 : 1'b0;
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//assign we = (pixel_counter==2'b11) ? 1'b1 : 1'b0;
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// -------------- grayscale image from YUV ------------------------
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/*
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assign o_data_wr = {y0[7:4],
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y0[7:4],
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y0[7:4]
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};
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*/
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//--------------- color RGB mode ---------------------------------
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assign o_data_wr = pixel_counter[1] ?
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{ byte1[7:4],
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{ byte1[2:0],byte2[7] },
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byte2[4:1]
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}
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:
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{ byte3[7:4],
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{ byte3[2:0],byte4[7] },
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byte4[4:1]
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};
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endmodule |