78 lines
1.7 KiB
Verilog
78 lines
1.7 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock input from top module
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "imag_transform.v"
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//top module
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`include "lookuptable.v"
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module imag_transform_tb#(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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)();
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//--------Internal register-----------
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reg clk = 1'b0;
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reg [CAM_LINE-1:0] r_line_cam = 0;
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reg [CAM_PIXEL-1:0] r_pixel_cam = 0;
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wire [CAM_LINE-1:0] r_line_out ;
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wire [CAM_PIXEL-1:0] r_pixel_out ;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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imag_transform #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) test_module (
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.clk(clk),
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.i_we(1'b1),
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.i_data(12'h0f0),
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.im_p(2'b01),
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.i_line(r_line_cam),
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.i_pixel(r_pixel_cam),
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.o_line(r_line_out),
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.o_pixel(r_pixel_out)
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);
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initial
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begin
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#0_000;
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r_line_cam = 'd203;
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r_pixel_cam = 'd403;
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#0_010;
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r_line_cam = 'd250;
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r_pixel_cam = 'd470;
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#0_010;
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r_line_cam = 'd40;
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r_pixel_cam = 'd120;
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#0_010;
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |