245 lines
7.1 KiB
Verilog
245 lines
7.1 KiB
Verilog
module imag_transform #(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10//,
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// TRA_IMG_WIDTH = 'd160,
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// TRA_IMG_DEPTH = 'd160,
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// T11 = 25'sb0_000000000001_011001100111,
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// T12 = 25'sb0_000000000000_001011001110,
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// T13 = 25'sb0_000000000000_000000001100,
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// T21 = 25'sb0_000000000000_000000000000,
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// T22 = 25'sb0_000000000000_111011101011,
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// T23 = 25'sb0_000000000000_000000000000,
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// T31 = 25'sb1_111000111111_111100111111,
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// T32 = 25'sb1_111110001111_111011100000,
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// T33 = 25'sb0_000000000001_000000000000
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) (
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input clk,
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input [1:0] im_p, // image processor controls
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// input form camera
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input i_we,
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input [CAM_DATA_WIDTH-1:0] i_data,
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input [CAM_LINE-1:0] i_line,
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input [CAM_PIXEL-1:0] i_pixel,
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// output
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output o_we,
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output [CAM_DATA_WIDTH-1:0] o_data,
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output [CAM_LINE-1:0] o_line,
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output [CAM_PIXEL-1:0] o_pixel,
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// image parameter output for address generator
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output [CAM_LINE-1:0] o_imag_depth,
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output [CAM_PIXEL-1:0] o_imag_width,
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output o_imag_resized,
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// parrameters of imag transform
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input [CAM_PIXEL-1:0] TRA_IMG_WIDTH ,
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input [CAM_LINE-1:0] TRA_IMG_DEPTH ,
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input [24:0] T11 ,
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input [24:0] T12 ,
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input [24:0] T13 ,
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input [24:0] T21 ,
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input [24:0] T22 ,
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input [24:0] T23 ,
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input [24:0] T31 ,
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input [24:0] T32 ,
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input [24:0] T33
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);
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//------------Internal variables and constants-----------
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(* KEEP = "TRUE" *) reg r_we1 = 0,
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r_we2 = 0,
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r_we3 = 0,
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r_we4 = 0,
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r_we5 = 0,
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r_we6 = 0,
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r_we7 = 0;
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(* KEEP = "TRUE" *) reg [CAM_DATA_WIDTH-1:0]
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r_data1 = 0,
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r_data2 = 0,
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r_data3 = 0,
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r_data4 = 0,
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r_data5 = 0,
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r_data6 = 0,
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r_data7 = 0;
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(* KEEP = "TRUE" *) reg signed [24:0]
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r_T11 = 0,
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r_T12 = 0,
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r_T13 = 0,
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r_T21 = 0,
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r_T22 = 0,
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r_T23 = 0,
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r_T31 = 0,
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r_T32 = 0,
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r_T33 = 0;
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(* KEEP = "TRUE" *) wire signed [11:0] w_w_inv;
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(* KEEP = "TRUE" *) reg [CAM_PIXEL-1:0] r_new_x = 0;
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(* KEEP = "TRUE" *) reg [CAM_LINE-1:0] r_new_y = 0;
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(* KEEP = "TRUE" *) reg signed [37:0]
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r_temp_x3 = 0,
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r_temp_y3 = 0;
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(* KEEP = "TRUE" *) reg signed [24:0]
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r_temp_w2 = 0,
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r_temp_x2 = 0,
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r_temp_y2 = 0;
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(* KEEP = "TRUE" *) reg signed [29:0]
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r_temp_x1 = 0,
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r_temp_y1 = 0,
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r_temp_w1 = 0;
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(* KEEP = "TRUE" *) reg signed [29:0]
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r_temp_summ11= 0,
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r_temp_summ21= 0,
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r_temp_summ31= 0;
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(* KEEP = "TRUE" *) reg signed [29:0]
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r_temp_summ12= 0,
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r_temp_summ22= 0,
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r_temp_summ32= 0;
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(* KEEP = "TRUE" *) reg signed [47:0]
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r_temp_11 = 0,
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r_temp_12 = 0,
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r_temp_13 = 0,
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r_temp_21 = 0,
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r_temp_22 = 0,
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r_temp_23 = 0,
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r_temp_31 = 0,
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r_temp_32 = 0,
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r_temp_33 = 0;
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(* KEEP = "TRUE" *) reg signed [CAM_PIXEL:0] r_x = 0;
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(* KEEP = "TRUE" *) reg signed [CAM_LINE :0] r_y = 0;
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(* KEEP = "TRUE" *) reg signed [1 :0] r_w = 0;
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//---------------pipeline--------------------------------
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always@(posedge clk) begin
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//----------------------------------7th cycle
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if (r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
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r_new_x <= 0;
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end else begin
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r_new_x <= r_temp_x3[20+CAM_PIXEL-1:20];
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end
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if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH) begin
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r_new_y <= 0;
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end else begin
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r_new_y <= r_temp_y3[20 + CAM_LINE-1:20];
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end
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r_data7 <= r_data6;
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if (r_temp_y3 < 0 || r_temp_y3[37:20] >= TRA_IMG_DEPTH ||
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r_temp_x3 < 0 || r_temp_x3[37:20] >= TRA_IMG_WIDTH) begin
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r_we7 <= 0;
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end else begin
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r_we7 <= r_we6;
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end
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//----------------------------------sixth cycle
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r_temp_x3 <= r_temp_x2 * w_w_inv; // 35bit
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r_temp_y3 <= r_temp_y2 * w_w_inv;
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r_data6 <= r_data5;
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r_we6 <= r_we5;
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//----------------------------------- fifth cycle
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r_temp_x2 <= r_temp_x1[24:0]; // resizing x value to fit 25x18bit multiplier
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r_temp_y2 <= r_temp_y1[24:0]; // resizing y value to fit 25x18bit multiplier
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r_temp_w2 <= r_temp_w1[24:0] ; //
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r_data5 <= r_data4;
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r_we5 <= r_we4;
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//----------------------------------- fourth cycle
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r_temp_x1 <= r_temp_summ11 + r_temp_summ12;
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r_temp_y1 <= r_temp_summ21 + r_temp_summ22;
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r_temp_w1 <= r_temp_summ31 + r_temp_summ32;
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r_data4 <= r_data3;
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r_we4 <= r_we3;
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//------------------------------------third cycle
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r_temp_summ11 <= r_temp_11 + r_temp_21;
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r_temp_summ12 <= r_temp_31;
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r_temp_summ21 <= r_temp_12 + r_temp_22;
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r_temp_summ22 <= r_temp_32;
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r_temp_summ31 <= r_temp_13 + r_temp_23;
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r_temp_summ32 <= r_temp_33;
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r_data3 <= r_data2;
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r_we3 <= r_we2;
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//-------------------------------------second cycle
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r_temp_11 <= r_x * r_T11;
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r_temp_21 <= r_y * r_T21;
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r_temp_31 <= r_w * r_T31;
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r_temp_12 <= r_x * r_T12;
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r_temp_22 <= r_y * r_T22;
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r_temp_32 <= r_w * r_T32;
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r_temp_13 <= r_x * r_T13;
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r_temp_23 <= r_y * r_T23;
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r_temp_33 <= r_w * r_T33;
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r_data2 <= r_data1;
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r_we2 <= r_we1;
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//-------------------------------------first cycle
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r_x <= i_pixel; // saves pixel coordinates in signed register
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r_y <= i_line;
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r_w <= 2'sd1;
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r_data1 <= i_data;
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r_we1 <= i_we;
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r_T11 <= T11;
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r_T12 <= T12;
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r_T13 <= T13;
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r_T21 <= T21;
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r_T22 <= T22;
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r_T23 <= T23;
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r_T31 <= T31;
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r_T32 <= T32;
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r_T33 <= T33;
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//-------------------------------------
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// matrix multiplication and new point coordinate calculation
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//
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// | T11 T12 T13 |
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// P [x,y,1] * T [3x3] = | x y 1 | * | T21 T22 T23 | = | x' y' w' |
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// | T31 T32 T33 |
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// | x' y'|
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// Pnew [x'',y''] = |---,---|
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// | w' w'|
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end
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//--------------------sub module------------------------
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lookuptable lookuptable(
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.clk(clk),
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.w(r_temp_w2[15:4]), // inputs calculated w value
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.r_w_inv(w_w_inv) // outputs inverted value from look up table
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);
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//------------ output logic------------------------------
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// assign o_we = (im_p == 2'b00)? i_we : r_we7;
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// assign o_data = (im_p == 2'b00)? i_data : r_data7;
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//
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// assign o_line = (im_p == 2'b00)? i_line : r_new_y;
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// assign o_pixel = (im_p == 2'b00)? i_pixel: r_new_x;
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//
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//
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// assign o_imag_depth = (im_p == 2'b00)? 'd480 : TRA_IMG_DEPTH;
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// assign o_imag_width = (im_p == 2'b00)? 'd640 : TRA_IMG_WIDTH;
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// assign o_imag_resized = (im_p == 2'b00)? 1'b0 : 1'b1;
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// output always resized and unsing transformation matrix.
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assign o_we = r_we7;
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assign o_data = r_data7;
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assign o_line = r_new_y;
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assign o_pixel = r_new_x;
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assign o_imag_depth = TRA_IMG_DEPTH;
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assign o_imag_width = TRA_IMG_WIDTH;
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assign o_imag_resized = 1'b1;
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endmodule |