279 lines
8.5 KiB
Verilog
279 lines
8.5 KiB
Verilog
module imag_procesor #(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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) (
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// control signals and clk --------
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input [8:0] im_p, // image processor controls
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input clk,
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input clk25,
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input clk50,
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input i_enable,
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// cam2 input-----------------------
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input i_we_cam2,
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input [CAM_DATA_WIDTH-1:0] i_data_cam2_wr,
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input [CAM_LINE-1:0] i_line_cam2,
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input [CAM_PIXEL-1:0] i_pixel_cam2,
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// cam1 input-----------------------
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input i_we_cam1,
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input [CAM_DATA_WIDTH-1:0] i_data_cam1_wr,
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input [CAM_LINE-1:0] i_line_cam1,
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input [CAM_PIXEL-1:0] i_pixel_cam1,
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// output---------------------------
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output o_we,
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output [16:0] o_addr_wr,
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output [CAM_DATA_WIDTH-1:0] o_data_wr,
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// to register RAM for imag transform
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input [24:0] i_data_reg,
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output [6:0] o_addr_rd_reg
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);
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//------- wire for rgb2gray----------------
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// cam1
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wire w_we_gray_cam1;
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wire [CAM_DATA_WIDTH-1:0] w_data_gray_cam1;
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wire [CAM_LINE-1:0] w_line_gray_cam1;
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wire [CAM_PIXEL-1:0] w_pixel_gray_cam1;
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// cam2
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wire w_we_gray_cam2;
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wire [CAM_DATA_WIDTH-1:0] w_data_gray_cam2;
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wire [CAM_LINE-1:0] w_line_gray_cam2;
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wire [CAM_PIXEL-1:0] w_pixel_gray_cam2;
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//------- wire for imag_transform------------
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// cam1
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wire w_we_it_cam1;
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wire [CAM_DATA_WIDTH-1:0] w_data_it_cam1;
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wire [CAM_LINE-1:0] w_line_it_cam1;
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wire [CAM_PIXEL-1:0] w_pixel_it_cam1;
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wire [CAM_LINE-1:0] w_imag_depth_cam1;
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wire [CAM_PIXEL-1:0] w_imag_width_cam1;
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wire w_imag_resized_cam1;
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// cam2
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wire w_we_it_cam2;
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wire [CAM_DATA_WIDTH-1:0] w_data_it_cam2;
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wire [CAM_LINE-1:0] w_line_it_cam2;
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wire [CAM_PIXEL-1:0] w_pixel_it_cam2;
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wire [CAM_LINE-1:0] w_imag_depth_cam2;
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wire [CAM_PIXEL-1:0] w_imag_width_cam2;
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wire w_imag_resized_cam2;
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//-----------wire for reg reader module
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// 1st camera
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wire [CAM_PIXEL-1:0] w_cam0_WIDTH;
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wire [CAM_LINE-1:0] w_cam0_DEPTH;
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wire [24:0] w_cam0_T11;
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wire [24:0] w_cam0_T12;
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wire [24:0] w_cam0_T13;
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wire [24:0] w_cam0_T21;
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wire [24:0] w_cam0_T22;
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wire [24:0] w_cam0_T23;
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wire [24:0] w_cam0_T31;
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wire [24:0] w_cam0_T32;
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wire [24:0] w_cam0_T33;
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// 2nd camera
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wire [CAM_PIXEL-1:0] w_cam1_WIDTH;
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wire [CAM_LINE-1:0] w_cam1_DEPTH;
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wire [24:0] w_cam1_T11;
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wire [24:0] w_cam1_T12;
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wire [24:0] w_cam1_T13;
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wire [24:0] w_cam1_T21;
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wire [24:0] w_cam1_T22;
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wire [24:0] w_cam1_T23;
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wire [24:0] w_cam1_T31;
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wire [24:0] w_cam1_T32;
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wire [24:0] w_cam1_T33;
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//---------- wire for save module -----------------
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wire [CAM_DATA_WIDTH-1:0] w_o_data_sw;
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wire w_o_we_sw;
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wire [16:0] w_o_addr_sw;
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//----------------------sub modules-------------------------------
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imag_save #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) imag_save(
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.clk(clk),
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.clk25(clk25),
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.clk50(clk50),
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.im_p(im_p[2:0]), // image processor controls
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//input
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//cam1
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.i_we_cam1( w_we_it_cam1),
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.i_data_cam1( w_data_it_cam1),
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.i_line_cam1( w_line_it_cam1),
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.i_pixel_cam1( w_pixel_it_cam1),
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.i_imag_depth_cam1(w_imag_depth_cam1),
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.i_imag_width_cam1(w_imag_width_cam1),
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.i_imag_resized_cam1(w_imag_resized_cam1),
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//cam2
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.i_we_cam2( w_we_it_cam2),
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.i_data_cam2( w_data_it_cam2),
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.i_line_cam2( w_line_it_cam2),
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.i_pixel_cam2( w_pixel_it_cam2),
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.i_imag_depth_cam2(w_imag_depth_cam2),
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.i_imag_width_cam2(w_imag_width_cam2),
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.i_imag_resized_cam2(w_imag_resized_cam2),
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//output
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.o_we( w_o_we_sw),
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.o_addr_wr( w_o_addr_sw),
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.o_data_wr( w_o_data_sw)
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);
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//------------------- gray or color-------------------------------
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rgb2gray #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) rgb2gray_cam1(
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.clk(clk),
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.gray(im_p[7]), // TRUE output gray
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.i_we( i_we_cam1),
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.i_data_wr( i_data_cam1_wr),
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.i_line( i_line_cam1),
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.i_pixel( i_pixel_cam1),
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.o_we( w_we_gray_cam1),
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.o_data_wr( w_data_gray_cam1),
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.o_line( w_line_gray_cam1),
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.o_pixel( w_pixel_gray_cam1)
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);
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rgb2gray #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) rgb2gray_cam2(
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.clk(clk),
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.gray(im_p[8]), // TRUE output gray
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.i_we( i_we_cam2),
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.i_data_wr( i_data_cam2_wr),
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.i_line( i_line_cam2),
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.i_pixel( i_pixel_cam2),
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.o_we( w_we_gray_cam2),
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.o_data_wr( w_data_gray_cam2),
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.o_line( w_line_gray_cam2),
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.o_pixel( w_pixel_gray_cam2)
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);
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//--------------------- original or transformed-------------------------
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imag_transform #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) imag_transform_cam1(
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.clk(clk),
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.im_p(im_p[4:3]), // image processor controls
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//input
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.i_we( w_we_gray_cam1),
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.i_data( w_data_gray_cam1),
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.i_line( w_line_gray_cam1),
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.i_pixel( w_pixel_gray_cam1),
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//output
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.o_we( w_we_it_cam1),
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.o_data( w_data_it_cam1),
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.o_line( w_line_it_cam1),
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.o_pixel( w_pixel_it_cam1),
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.o_imag_depth(w_imag_depth_cam1),
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.o_imag_width(w_imag_width_cam1),
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.o_imag_resized(w_imag_resized_cam1),
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// imag transform parmeters
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.TRA_IMG_WIDTH (w_cam0_WIDTH),
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.TRA_IMG_DEPTH (w_cam0_DEPTH),
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.T11 (w_cam0_T11),
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.T12 (w_cam0_T12),
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.T13 (w_cam0_T13),
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.T21 (w_cam0_T21),
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.T22 (w_cam0_T22),
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.T23 (w_cam0_T23),
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.T31 (w_cam0_T31),
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.T32 (w_cam0_T32),
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.T33 (w_cam0_T33)
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);
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imag_transform #(
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.CAM_DATA_WIDTH(CAM_DATA_WIDTH),
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) imag_transform_cam2(
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.clk(clk),
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.im_p(im_p[6:5]), // image processor controls
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//input
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.i_we( w_we_gray_cam2),
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.i_data( w_data_gray_cam2),
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.i_line( w_line_gray_cam2),
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.i_pixel( w_pixel_gray_cam2),
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//output
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.o_we( w_we_it_cam2),
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.o_data( w_data_it_cam2),
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.o_line( w_line_it_cam2),
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.o_pixel( w_pixel_it_cam2),
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.o_imag_depth(w_imag_depth_cam2),
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.o_imag_width(w_imag_width_cam2),
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.o_imag_resized(w_imag_resized_cam2),
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// imag transform parmeters
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.TRA_IMG_WIDTH (w_cam1_WIDTH),
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.TRA_IMG_DEPTH (w_cam1_DEPTH),
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.T11 (w_cam1_T11),
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.T12 (w_cam1_T12),
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.T13 (w_cam1_T13),
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.T21 (w_cam1_T21),
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.T22 (w_cam1_T22),
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.T23 (w_cam1_T23),
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.T31 (w_cam1_T31),
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.T32 (w_cam1_T32),
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.T33 (w_cam1_T33)
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);
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reg_reader #(
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.CAM_LINE(CAM_LINE),
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.CAM_PIXEL(CAM_PIXEL)
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) reg_reader1 (
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.clk(clk),
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.i_enable(i_enable),
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.i_cam0_mode(im_p[4:3]),
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.i_cam1_mode(im_p[6:5]),
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.i_data(i_data_reg),
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.o_addr_rd(o_addr_rd_reg),
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// 1st camera
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.o_cam0_WIDTH(w_cam0_WIDTH),
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.o_cam0_DEPTH(w_cam0_DEPTH),
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.o_cam0_T11(w_cam0_T11),
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.o_cam0_T12(w_cam0_T12),
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.o_cam0_T13(w_cam0_T13),
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.o_cam0_T21(w_cam0_T21),
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.o_cam0_T22(w_cam0_T22),
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.o_cam0_T23(w_cam0_T23),
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.o_cam0_T31(w_cam0_T31),
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.o_cam0_T32(w_cam0_T32),
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.o_cam0_T33(w_cam0_T33),
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// 2nd camera
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.o_cam1_WIDTH(w_cam1_WIDTH),
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.o_cam1_DEPTH(w_cam1_DEPTH),
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.o_cam1_T11(w_cam1_T11),
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.o_cam1_T12(w_cam1_T12),
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.o_cam1_T13(w_cam1_T13),
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.o_cam1_T21(w_cam1_T21),
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.o_cam1_T22(w_cam1_T22),
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.o_cam1_T23(w_cam1_T23),
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.o_cam1_T31(w_cam1_T31),
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.o_cam1_T32(w_cam1_T32),
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.o_cam1_T33(w_cam1_T33)
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);
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//------------------- output logic -----------------------------------
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assign o_data_wr = w_o_data_sw ;
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assign o_we = w_o_we_sw ;
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assign o_addr_wr = w_o_addr_sw;
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endmodule
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