73 lines
2.1 KiB
Verilog
73 lines
2.1 KiB
Verilog
module horizontal_counter #(
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parameter
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HSYNC_CLKS = 800,
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HSYNC_DISPLAY = 640,
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HSYNC_PULSE = 96,
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HSYNC_FRONT_PORCH = 16,
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HSYNC_BACK_PORCH = 48
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)(
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input clk,
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output o_Hsync,
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output o_h_display,
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output [9:0] o_h_pixel
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);
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//----------Internal registers, constants and wariables-----
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reg hsync_reg = 1'b1;
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reg [9:0] counter_reg = 'h0;
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reg [9:0] counter_pixel_reg = 'h0;
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reg [2:0] r_state=HS_FRONT_PORCH, r_next=HS_FRONT_PORCH;
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localparam [2:0] HS_FRONT_PORCH = 'h0,
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HS_PULSE = 'h1,
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HS_BACK_PORCH = 'h2,
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HS_DISPLAY = 'h3;
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//---------state register sequential always block-----------
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always @(posedge clk ) begin
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r_state <= r_next;
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end
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//----next state & outputs, combinational always block------
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always@(posedge clk) begin
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counter_reg <= counter_reg + 1;
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case (r_state)
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HS_FRONT_PORCH: begin
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hsync_reg <= 1'b1;
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if(counter_reg == HSYNC_FRONT_PORCH - 2)
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r_next <= HS_PULSE;
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end
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HS_PULSE:begin
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hsync_reg <= 1'b0;
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if(counter_reg == HSYNC_FRONT_PORCH +
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HSYNC_PULSE - 2)
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r_next <= HS_BACK_PORCH;
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end
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HS_BACK_PORCH:begin
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hsync_reg <= 1'b1;
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if(counter_reg == HSYNC_FRONT_PORCH +
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HSYNC_PULSE +
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HSYNC_BACK_PORCH - 2) begin
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r_next <= HS_DISPLAY;
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counter_pixel_reg <= 'h0;
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end
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end
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HS_DISPLAY:begin
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hsync_reg <= 1'b1;
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counter_pixel_reg <= counter_pixel_reg + 1;
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if(counter_reg == HSYNC_FRONT_PORCH +
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HSYNC_PULSE +
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HSYNC_BACK_PORCH +
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HSYNC_DISPLAY - 1) begin
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r_next <= HS_FRONT_PORCH;
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counter_reg <= 'h0;
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end
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end
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endcase
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end
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assign o_Hsync = hsync_reg;
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assign o_h_display = (counter_pixel_reg >= 1 && counter_pixel_reg <= HSYNC_DISPLAY) ? 1'b1 : 1'b0 ;
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assign o_h_pixel = counter_pixel_reg - 1 ;
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endmodule |