67 lines
1.3 KiB
Verilog
67 lines
1.3 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock input from top module
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//sub modules
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`include "clock_enable_param.v"
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//top module
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`include "default_reg_writer.v"
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module default_reg_writer_tb();
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//--------Internal register-----------
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reg clk = 1'b0;
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wire w_enable;
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reg reset = 0;
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//---------Test script----------------
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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//-----Unit Under test---------------
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default_reg_writer uut_sender(
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.clk(clk),
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.i_enable(w_enable),
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.i_reset(reset)
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);
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clock_enable_param #(
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// .WAIT(WAIT),
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// .WIDTH(WAIT_WIDTH)
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) clock_enable1 (
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.clk(clk),
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.enable(w_enable)
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);
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initial
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begin
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#0_500;
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$display("*");
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reset = 1;
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#0_020;
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reset = 0;
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#0_500;
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |