465 lines
22 KiB
Verilog
465 lines
22 KiB
Verilog
// Default parameters for image transform module
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// Four MSB are actual registers
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// next two bits are one of modes selected by swishes. 4 modes are avilable
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// LSB are camera bit. avilable two cameras. Camera 0 and camera 1.
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//
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//
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module default_reg_writer #(parameter
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CAM_LINE = 9,
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CAM_PIXEL = 10,
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// default settings for mode 0 camera 0
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TRA_IMG_WIDTH_0_0 = 'd320,
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TRA_IMG_DEPTH_0_0 = 'd240,
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T11_0_0 = 25'sb0_000000000000_100000000000,
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T12_0_0 = 25'sb0_000000000000_000000000000,
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T13_0_0 = 25'sb0_000000000000_000000000000,
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T21_0_0 = 25'sb0_000000000000_000000000000,
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T22_0_0 = 25'sb0_000000000000_100000000000,
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T23_0_0 = 25'sb0_000000000000_000000000000,
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T31_0_0 = 25'sb0_000000000000_000000000000,
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T32_0_0 = 25'sb0_000000000000_000000000000,
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T33_0_0 = 25'sb0_000000000001_000000000000,
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// default settings for mode 0 camera 1
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TRA_IMG_WIDTH_0_1 = 'd320,
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TRA_IMG_DEPTH_0_1 = 'd240,
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T11_0_1 = 25'sb0_000000000000_100000000000,
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T12_0_1 = 25'sb0_000000000000_000000000000,
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T13_0_1 = 25'sb0_000000000000_000000000000,
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T21_0_1 = 25'sb0_000000000000_000000000000,
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T22_0_1 = 25'sb0_000000000000_100000000000,
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T23_0_1 = 25'sb0_000000000000_000000000000,
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T31_0_1 = 25'sb0_000000000000_000000000000,
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T32_0_1 = 25'sb0_000000000000_000000000000,
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T33_0_1 = 25'sb0_000000000001_000000000000,
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// default settings for mode 1 camera 0
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TRA_IMG_WIDTH_1_0 = 'd320,
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TRA_IMG_DEPTH_1_0 = 'd240,
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T11_1_0 = 25'sh0000000,
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T12_1_0 = 25'sh1fffa04,
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T13_1_0 = 25'sh0000000,
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T21_1_0 = 25'sh0000aa8,
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T22_1_0 = 25'sh0000000,
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T23_1_0 = 25'sh0000000,
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T31_1_0 = 25'sh0000000,
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T32_1_0 = 25'sh00ef000,
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T33_1_0 = 25'sh0001000,
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// default settings for mode 1 camera 1
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TRA_IMG_WIDTH_1_1 = 'd320,
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TRA_IMG_DEPTH_1_1 = 'd240,
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T11_1_1 = 25'sh0000000,
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T12_1_1 = 25'sh1fffa04,
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T13_1_1 = 25'sh0000000,
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T21_1_1 = 25'sh0000aa8,
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T22_1_1 = 25'sh0000000,
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T23_1_1 = 25'sh0000000,
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T31_1_1 = 25'sh0000000,
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T32_1_1 = 25'sh00ef000,
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T33_1_1 = 25'sh0001000,
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// default settings for mode 2 camera 0
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TRA_IMG_WIDTH_2_0 = 'd320,
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TRA_IMG_DEPTH_2_0 = 'd240,
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T11_2_0 = 25'sh1fff803,
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T12_2_0 = 25'sh0000000,
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T13_2_0 = 25'sh0000000,
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T21_2_0 = 25'sh0000000,
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T22_2_0 = 25'sh1fff804,
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T23_2_0 = 25'sh0000000,
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T31_2_0 = 25'sh013f000,
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T32_2_0 = 25'sh00ef000,
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T33_2_0 = 25'sh0001000,
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// default settings for mode 2 camera 1
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TRA_IMG_WIDTH_2_1 = 'd320,
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TRA_IMG_DEPTH_2_1 = 'd240,
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T11_2_1 = 25'sh1fff803,
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T12_2_1 = 25'sh0000000,
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T13_2_1 = 25'sh0000000,
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T21_2_1 = 25'sh0000000,
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T22_2_1 = 25'sh1fff804,
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T23_2_1 = 25'sh0000000,
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T31_2_1 = 25'sh013f000,
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T32_2_1 = 25'sh00ef000,
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T33_2_1 = 25'sh0001000,
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// default settings for mode 3 camera 0
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TRA_IMG_WIDTH_3_0 = 'd320,
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TRA_IMG_DEPTH_3_0 = 'd240,
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T11_3_0 = 25'sh0000000,
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T12_3_0 = 25'sh00005fc,
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T13_3_0 = 25'sh0000000,
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T21_3_0 = 25'sh1fff558,
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T22_3_0 = 25'sh0000000,
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T23_3_0 = 25'sh0000000,
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T31_3_0 = 25'sh013f000,
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T32_3_0 = 25'sh0000000,
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T33_3_0 = 25'sh0001000,
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// default settings for mode 3 camera 1
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TRA_IMG_WIDTH_3_1 = 'd320,
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TRA_IMG_DEPTH_3_1 = 'd240,
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T11_3_1 = 25'sh0000000,
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T12_3_1 = 25'sh00005fc,
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T13_3_1 = 25'sh0000000,
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T21_3_1 = 25'sh1fff558,
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T22_3_1 = 25'sh0000000,
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T23_3_1 = 25'sh0000000,
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T31_3_1 = 25'sh013f000,
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T32_3_1 = 25'sh0000000,
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T33_3_1 = 25'sh0001000
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)(
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input clk,
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input i_enable,
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input i_reset,
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output o_configured,
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output [6:0] o_addr ,
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output [24:0] o_data ,
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output o_we
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);
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// Internal variables and registers
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reg r_configured = 0;
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reg [6:0] r_divider = 7'b0000001; // this value gives a 127 cycle pause before the initial frame is sent
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reg [6:0] r_count = 'b0;
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reg [24:0] r_data = 'b0;
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reg r_we = 'b0;
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//------------------ synchonus logic------------------
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always @ (posedge clk) begin
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if(i_enable)begin
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if (i_reset || r_divider != 0 ) begin
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r_count <= 0;
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r_divider <= r_divider + 1;
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r_configured <= 0;
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if (r_divider == 'd127) r_we <= 1;
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else r_we <= 0;
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end
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else if ( r_count < 88 ) begin
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r_count <= r_count + 1;
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r_we <= 1;
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end
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end
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case (r_count[6:3]) // select parameter
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'd0 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_0_0;
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'd1 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_1_0;
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'd1 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_2_0;
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'd1 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_3_0;
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'd1 : r_data[CAM_PIXEL-1:0] <= TRA_IMG_WIDTH_3_1;
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endcase
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end
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endcase
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end
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'd1 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_0_0;
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'd1 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_1_0;
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'd1 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_2_0;
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'd1 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_3_0;
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'd1 : r_data[CAM_LINE-1:0] <= TRA_IMG_DEPTH_3_1;
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endcase
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end
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endcase
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end
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'd2 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T11_0_0;
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'd1 : r_data <= T11_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T11_1_0;
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'd1 : r_data <= T11_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T11_2_0;
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'd1 : r_data <= T11_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T11_3_0;
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'd1 : r_data <= T11_3_1;
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endcase
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end
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endcase
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end
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'd3 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T12_0_0;
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'd1 : r_data <= T12_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T12_1_0;
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'd1 : r_data <= T12_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T12_2_0;
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'd1 : r_data <= T12_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T12_3_0;
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'd1 : r_data <= T12_3_1;
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endcase
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end
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endcase
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end
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'd4 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T13_0_0;
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'd1 : r_data <= T13_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T13_1_0;
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'd1 : r_data <= T13_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T13_2_0;
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'd1 : r_data <= T13_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T13_3_0;
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'd1 : r_data <= T13_3_1;
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endcase
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end
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endcase
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end
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'd5 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T21_0_0;
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'd1 : r_data <= T21_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T21_1_0;
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'd1 : r_data <= T21_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T21_2_0;
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'd1 : r_data <= T21_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T21_3_0;
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'd1 : r_data <= T21_3_1;
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endcase
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end
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endcase
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end
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'd6 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T22_0_0;
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'd1 : r_data <= T22_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T22_1_0;
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'd1 : r_data <= T22_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T22_2_0;
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'd1 : r_data <= T22_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T22_3_0;
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'd1 : r_data <= T22_3_1;
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endcase
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end
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endcase
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end
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'd7 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T23_0_0;
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'd1 : r_data <= T23_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T23_1_0;
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'd1 : r_data <= T23_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T23_2_0;
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'd1 : r_data <= T23_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T23_3_0;
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'd1 : r_data <= T23_3_1;
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endcase
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end
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endcase
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end
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'd8 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T31_0_0;
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'd1 : r_data <= T31_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T31_1_0;
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'd1 : r_data <= T31_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T31_2_0;
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'd1 : r_data <= T31_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T31_3_0;
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'd1 : r_data <= T31_3_1;
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endcase
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end
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endcase
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end
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'd9 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T32_0_0;
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'd1 : r_data <= T32_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T32_1_0;
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'd1 : r_data <= T32_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T32_2_0;
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'd1 : r_data <= T32_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T32_3_0;
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'd1 : r_data <= T32_3_1;
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endcase
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end
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endcase
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end
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'd10 : begin
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case (r_count[2:1]) // select mode
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'd0 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T33_0_0;
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'd1 : r_data <= T33_0_1;
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endcase
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end
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'd1 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T33_1_0;
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'd1 : r_data <= T33_1_1;
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endcase
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end
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'd2 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T33_2_0;
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'd1 : r_data <= T33_2_1;
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endcase
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end
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'd3 : begin
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case (r_count[0]) // select camera
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'd0 : r_data <= T33_3_0;
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'd1 : r_data <= T33_3_1;
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endcase
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end
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endcase
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end
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default: begin
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r_configured <= 1; // default case just in case do nothing
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r_we <= 0;
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end
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endcase
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end
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//----------- combinational logic ----------------------
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assign o_configured = r_configured;
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assign o_addr = r_count;
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assign o_data = r_data;
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assign o_we = r_we;
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endmodule |