95 lines
2.0 KiB
Verilog
95 lines
2.0 KiB
Verilog
// This module is based on Top module: com_to_mem_top.v
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// recive comand, addres and data by
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// UART and write information in Block RAM
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//`include "clock_divider_param.v"
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//`include "clock_enable_param.v"
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//`include "7segment_v2.v"
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//`include "com_to_mem_FSM.v"
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//`include "UART_Loopback_module.v"
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module com_to_mem #( parameter
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WAIT = 1,
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WAIT_WIDTH = 2,
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ADDR_WIDTH = 17,
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DATA_WIDTH = 8,
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DEPTH = 76_800
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)(
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input clk,
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input sw,
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input i_enable,
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// input [DATA_WIDTH-1:0] i_data_rd,
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input RsRx, // UART RX Data
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output RsTx, // UART TX Data
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output [6:0] seg,
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output [3:0] an,
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// output dp,
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output [ADDR_WIDTH-1:0] o_addr_wr,
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output [ADDR_WIDTH-1:0] o_addr_rd,
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output [DATA_WIDTH-1:0] o_data_wr,
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output o_write ,
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output [6:0] o_addr_wr_reg,
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output [24:0] o_data_reg,
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output o_we_reg
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);
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wire clk10k;
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wire [7:0] w_dout;
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wire w_RX_DV;
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wire w_TX_Done;
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wire [3:0] w_state;
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wire [3:0] w_byte;
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//------ instatiated modules ---------------------------
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com_to_mem_FSM #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH)
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) FSM1(
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.clk(clk),
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.i_enable(i_enable),
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.din(w_dout),
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.TX_Done(w_TX_Done),
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.i_RX_DV(w_RX_DV),
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.addr_wr(o_addr_wr),
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.addr_rd(o_addr_rd),
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.data_wr(o_data_wr),
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.write(o_write),
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.o_state(w_state),
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.o_byte(w_byte),
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.o_addr_wr_reg(o_addr_wr_reg),
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.o_data_reg(o_data_reg),
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.o_we_reg(o_we_reg)
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);
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bin_7segment bin_7segment1(
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.clk(clk10k),
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.sw({w_state, w_byte, w_dout}),
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.seg(seg),
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.an(an),
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.dp());
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UART_Loopback_module #(
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.DATA_WIDTH('d8)
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) UART_Loopback_module1
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( .clk(clk),
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.loopback(sw),
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.RsRx(RsRx),
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.RsTx(RsTx),
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.dout(w_dout),
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.o_TX_Done(w_TX_Done),
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.o_RX_DV(w_RX_DV));
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clock_divider #(
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.DIVIDER(1_000),
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.WIDTH(24)
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) clock_divider7seg (
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.clk(clk),
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.clk_out(clk10k)
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);
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endmodule |