31 lines
516 B
Verilog
31 lines
516 B
Verilog
// This module devide FPGA input clock
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// by DIVIDER.
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//
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//
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module clock_enable_param #(
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parameter WAIT =1,
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parameter WIDTH =1
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) (
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input clk,
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output enable);
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reg state=1'b0;
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reg [WIDTH-1:0] counter = 1'b0 ;
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always@(posedge clk)begin
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if(counter == 0)begin
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if (state == 1) begin
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state <= 0;
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counter <= WAIT - 1;
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end
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else begin
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state <= 1;
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counter <= 0;
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end
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end
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else counter <= counter -1;
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end
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assign enable = state;
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endmodule |