28 lines
537 B
Verilog
28 lines
537 B
Verilog
// This module devide FPGA input clock
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// by DIVIDER. Result is 50% duty cicle
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// pulses.
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//
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//
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module clock_divider #(
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parameter DIVIDER =2,
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parameter WIDTH =2
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) (
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input clk,
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output clk_out);
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reg state=1'b0, next_state=1'b1;
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reg [WIDTH-1:0] counter = DIVIDER-1 ;
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always@(posedge clk)begin
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state <= next_state;
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if ( counter == 0) begin
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next_state <= ~next_state;
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counter <= DIVIDER-1;
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end
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else if (counter >= 0 )
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counter <= counter - 1;
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end
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assign clk_out = state;
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endmodule |