82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
// This module generate address for main memmory, where pixel data will be saved.
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//
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module address_gen#(
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parameter CAM_DATA_WIDTH = 12,
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CAM_LINE = 9,
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CAM_PIXEL = 10
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) (
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input clk,
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// inputs from camera (or transdormed image)
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input i_we,
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input [CAM_DATA_WIDTH-1:0] i_data,
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input [CAM_LINE-1:0] i_line,
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input [CAM_PIXEL-1:0] i_pixel,
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// image size and does it need to be resized
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input [CAM_LINE-1:0] i_imag_depth,
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input [CAM_PIXEL-1:0] i_imag_width,
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// input i_imag_resized,
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// outputs
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output o_we,
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output [CAM_DATA_WIDTH-1:0] o_data,
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output [16:0] o_addr
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);
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//------------Internal variables and constants-----------
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reg r_we1 = 0;
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reg r_we2 = 0;
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reg [16:0] r_addr_wr1 = 0;
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reg [16:0] r_addr_wr2 = 0;
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reg [CAM_DATA_WIDTH-1:0] r_data1 = 0;
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reg [CAM_DATA_WIDTH-1:0] r_data2 = 0;
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reg [CAM_PIXEL-1:0] r_pixel1 = 0;
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// reg [CAM_PIXEL-1:0] r_pixel2 = 0;
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reg [CAM_LINE-1:0] r_line1 = 0;
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// reg [CAM_LINE-1:0] r_line2 = 0;
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//---------------------------------------------------------
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always @(posedge clk) begin
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// second cycle
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if (r_pixel1 < i_imag_width && r_line1 < i_imag_depth ) begin
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r_we2 <= r_we1;
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// r_line2 <= r_line1;
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// r_pixel2 <= r_pixel1;
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r_data2 <= r_data1;
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r_addr_wr2 <= r_addr_wr1 + r_pixel1[CAM_PIXEL-1:0];
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end
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else begin
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r_we2 <= 'h0;
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// r_line2 <= 'h0;
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// r_pixel2 <= 'h0;
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r_data2 <= 'h0;
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r_addr_wr2 <= 'h0;
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end
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// first cycle
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if (i_pixel < i_imag_width && i_line < i_imag_depth ) begin
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r_we1 <= i_we;
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r_line1 <= i_line;
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r_pixel1 <= i_pixel;
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r_data1 <= i_data;
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r_addr_wr1 <= i_line[CAM_LINE-1:0] * 'd320;
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end
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else begin
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r_we1 <= 'h0;
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r_line1 <= 'h0;
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r_pixel1 <= 'h0;
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r_data1 <= 'h0;
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r_addr_wr1 <= 'h0;
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end
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end
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assign o_we = r_we2 ;
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assign o_data = r_data2 ;
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assign o_addr = r_addr_wr2 ;
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endmodule |