44 lines
1.0 KiB
Verilog
44 lines
1.0 KiB
Verilog
//
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// Original file donwloaded from nandland.com
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//
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// Outputs byte received from UART
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//
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//`include "UART_RX.v"
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//`include "UART_TX.v"
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module UART_Loopback_module #( parameter
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DATA_WIDTH = 8
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)
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( input clk, // Main Clock
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input loopback,
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input RsRx, // UART RX Data
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output RsTx, // UART TX Data
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output [DATA_WIDTH-1:0] dout, // data out
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output o_TX_Done, // high when transition is done
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output o_RX_DV // data valid
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);
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wire w_TX_Active, w_TX_Serial;
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wire [DATA_WIDTH-1:0] w_RX_Byte;
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UART_RX #(.CLKS_PER_BIT(868)) UART_RX_Inst
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(.clk(clk),
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.RsRx(RsRx),
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.o_RX_DV(o_RX_DV),
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.o_RX_Byte(w_RX_Byte));
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UART_TX #(.CLKS_PER_BIT(868)) UART_TX_Inst
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(.clk(clk),
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.i_TX_DV(o_RX_DV),
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.i_TX_Byte(w_RX_Byte),
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.o_TX_Active(w_TX_Active),
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.o_TX_Serial(w_TX_Serial),
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.o_TX_Done(o_TX_Done));
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// drive UART line high when transmiter not active
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assign RsTx = (w_TX_Active && loopback) ? w_TX_Serial : 1'b1;
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assign dout = w_RX_Byte;
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endmodule |