Demo mode added

2019-10-20 13:49:07 +03:00
parent fc3b11c78e
commit f44880bc30
5 changed files with 60 additions and 282 deletions
@@ -68,7 +68,7 @@ module top #( parameter
    output [3:0]    vgaGreen,
    output          Hsync,
    output          Vsync,
-    input [2:0]     sw,
+    input [3:0]     sw,
    input [8:0]     im_p,
    //UART 
    input           RsRx,         // UART RX Data
@@ -159,6 +159,8 @@ module top #( parameter
  wire [24:0]             w_data_com_reg ;
  wire                    w_we_com_reg ;

+  wire [8:0]              w_im_p;
+
 //-----sub modules--------------------------
 clock_enable_param #(
    .WAIT(WAIT),
@@ -321,7 +323,7 @@ imag_procesor #(
    .CAM_LINE(CAM_LINE),
    .CAM_PIXEL(CAM_PIXEL)
 ) imag_procesor(
-    .im_p(im_p),
+    .im_p(w_im_p),
    .clk(clk),
    .clk25(pixel_clk),
    .clk50(clk50),
@@ -379,6 +381,14 @@ debounce_switch debounce_switch_reset(
    .o_switch(w_reset_default)
 );

+mode_selector mode_selector(
+    .clk(clk),
+ //   .i_enable(w_enable),
+    .i_im_p(im_p),
+    .autoselect(sw[3]),
+    .o_im_p(w_im_p)
+);
+

 always@(posedge clk) begin
        if (~w_wea_bram) begin