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Imants Pulkstenis
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// Default parameters for image transform module
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// Four MSB are actual registers
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// next two bits are one of modes selected by swishes. 4 modes are avilable
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// LSB are camera bit. avilable two cameras. Camera 0 and camera 1.
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//
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//
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module reg_reader #(parameter
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CAM_LINE = 9,
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CAM_PIXEL = 10//,
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)(
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input clk,
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input i_enable,
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input [24:0] i_data,
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output [6:0] o_addr_rd,
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// camera modes from input swiches
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input [1:0] i_cam0_mode,
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input [1:0] i_cam1_mode,
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// 1st camera
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output [CAM_PIXEL-1:0] o_cam0_WIDTH,
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output [CAM_LINE-1:0] o_cam0_DEPTH,
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output [24:0] o_cam0_T11,
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output [24:0] o_cam0_T12,
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output [24:0] o_cam0_T13,
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output [24:0] o_cam0_T21,
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output [24:0] o_cam0_T22,
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output [24:0] o_cam0_T23,
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output [24:0] o_cam0_T31,
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output [24:0] o_cam0_T32,
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output [24:0] o_cam0_T33,
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// 2nd camera
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output [CAM_PIXEL-1:0] o_cam1_WIDTH,
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output [CAM_LINE-1:0] o_cam1_DEPTH,
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output [24:0] o_cam1_T11,
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output [24:0] o_cam1_T12,
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output [24:0] o_cam1_T13,
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output [24:0] o_cam1_T21,
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output [24:0] o_cam1_T22,
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output [24:0] o_cam1_T23,
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output [24:0] o_cam1_T31,
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output [24:0] o_cam1_T32,
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output [24:0] o_cam1_T33
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);
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// Internal variables and registers
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reg [6:0] r_count = 'b0;
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reg [24:0] r_data = 'b0;
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reg [CAM_PIXEL-1:0] r_cam0_WIDTH = 'b0;// 'd320;
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reg [CAM_LINE-1:0] r_cam0_DEPTH = 'b0;// 'd240;
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reg [24:0] r_cam0_T11 = 'b0;// 25'b0_000000000000_100000000000;
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reg [24:0] r_cam0_T12 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T13 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T21 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T22 = 'b0;// 25'b0_000000000000_100000000000;
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reg [24:0] r_cam0_T23 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T31 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T32 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam0_T33 = 'b0;// 25'b0_000000000001_000000000000;
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reg [CAM_PIXEL-1:0] r_cam1_WIDTH = 'b0;// 'd320;
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reg [CAM_LINE-1:0] r_cam1_DEPTH = 'b0;// 'd240;
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reg [24:0] r_cam1_T11 = 'b0;// 25'b0_000000000000_100000000000;
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reg [24:0] r_cam1_T12 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T13 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T21 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T22 = 'b0;// 25'b0_000000000000_100000000000;
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reg [24:0] r_cam1_T23 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T31 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T32 = 'b0;// 25'b0_000000000000_000000000000;
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reg [24:0] r_cam1_T33 = 'b0;// 25'b0_000000000001_000000000000;
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//--------------------------- synchonus logic------------------
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always @ (posedge clk) begin
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if(i_enable)begin
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r_count <= r_count + 1;
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end
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if(i_enable) begin
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case (r_count[0])
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'b0 : begin
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case (r_count[6:3])
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'd0 : r_cam0_WIDTH <= i_data[CAM_PIXEL-1:0];
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'd1 : r_cam0_DEPTH <= i_data[CAM_LINE-1:0];
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'd2 : r_cam0_T11 <= i_data;
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'd3 : r_cam0_T12 <= i_data;
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'd4 : r_cam0_T13 <= i_data;
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'd5 : r_cam0_T21 <= i_data;
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'd6 : r_cam0_T22 <= i_data;
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'd7 : r_cam0_T23 <= i_data;
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'd8 : r_cam0_T31 <= i_data;
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'd9 : r_cam0_T32 <= i_data;
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'd10 : r_cam0_T33 <= i_data;
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default: ;
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endcase
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end
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'b1 : begin
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case (r_count[6:3])
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'd0 : r_cam1_WIDTH <= i_data[CAM_PIXEL-1:0];
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'd1 : r_cam1_DEPTH <= i_data[CAM_LINE-1:0];
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'd2 : r_cam1_T11 <= i_data;
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'd3 : r_cam1_T12 <= i_data;
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'd4 : r_cam1_T13 <= i_data;
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'd5 : r_cam1_T21 <= i_data;
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'd6 : r_cam1_T22 <= i_data;
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'd7 : r_cam1_T23 <= i_data;
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'd8 : r_cam1_T31 <= i_data;
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'd9 : r_cam1_T32 <= i_data;
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'd10 : r_cam1_T33 <= i_data;
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default: ;
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endcase
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end
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endcase
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end
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end
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//------------------ combinational logic ----------------------
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assign o_addr_rd = {r_count[6:3], (r_count[0])? i_cam1_mode : i_cam0_mode , r_count[0] };
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// 1st camera
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assign o_cam0_WIDTH = r_cam0_WIDTH;
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assign o_cam0_DEPTH = r_cam0_DEPTH;
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assign o_cam0_T11 = r_cam0_T11;
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assign o_cam0_T12 = r_cam0_T12;
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assign o_cam0_T13 = r_cam0_T13;
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assign o_cam0_T21 = r_cam0_T21;
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assign o_cam0_T22 = r_cam0_T22;
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assign o_cam0_T23 = r_cam0_T23;
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assign o_cam0_T31 = r_cam0_T31;
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assign o_cam0_T32 = r_cam0_T32;
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assign o_cam0_T33 = r_cam0_T33;
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// 2nd camera
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assign o_cam1_WIDTH = r_cam1_WIDTH;
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assign o_cam1_DEPTH = r_cam1_DEPTH;
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assign o_cam1_T11 = r_cam1_T11;
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assign o_cam1_T12 = r_cam1_T12;
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assign o_cam1_T13 = r_cam1_T13;
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assign o_cam1_T21 = r_cam1_T21;
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assign o_cam1_T22 = r_cam1_T22;
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assign o_cam1_T23 = r_cam1_T23;
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assign o_cam1_T31 = r_cam1_T31;
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assign o_cam1_T32 = r_cam1_T32;
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assign o_cam1_T33 = r_cam1_T33;
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endmodule
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